mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 85

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

12.3
In order to meet PRI Layer 1 requirements and to assist in circuit fault sectionalization, the MT9072 has 7 loopback
functions.
Table 40 specifies the registers related to controlling the different loopbacks.
a) Digital loopback (DG Loop) - DSTi to DSTo at the PCM30 side. Bit DLBK = 0 normal; DLBK = 1 activate.
The control bits for digital, remote, ST-BUS and payload loopbacks are located at address Y05. The remote and
local timeslot loopbacks are controlled through control bits of the Timeslot Control register located at addresses
Y90-YAF.
b) Payload loopback (PL Loop) - Payload loopback (DSTo to DSTi). Bit PLBK = 0 normal; PLBK = 1 activate. The
payload loopback is effectively a physical connection of DSTo to DSTi within the MT9072.
Register
Address
Y90 to YAF
System
Register
Address
Y35
Y45
System
Y01
Y02
904
E1 Loopbacks
DSTo
DSTo
DSTi
DSTi
Receive Line and Timer
Interrupt Status
Receive Line and Timer
Interrupt Mask
Test, Error and Loopback
Control Register
Interrupt and IO control register RxDO and RxCO have to one for certain loopbacks to work.
Timeslot Control Register
Framer Loopback Global
Register
Register
MT9072
MT9072
Table 40 - Register Related to Setting Up Loopbacks (E1)
Table 39 - Registers Related to In Band Loopbacks (T1)
Register
LLEI and LLDI are the interrupts for LLED and LLDD.
LLEIM and LLDIM are the masks for LLEI and LLDI.
Tx
Rx
Tx
PCM30
PCM30
Zarlink Semiconductor Inc.
The bits DLBK,RLBK, SLBK and PLBK can be used for digital
loopback, remote loopback, ST-BUS and loopback.
Local and Remote Timeslot Control Register allows for Timeslot
Loopbacks (RTSLand TTSL).
Framer to Framer ST-BUS and Remote Loopbacks.
MT9072
85
Description
Description
Data Sheet