mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 142

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

17.1.8
Tables 112 to 114 provide the per timeslot control for signaling and Per Channel Control. The reset values of Per
channel Transmit signaling and Receive signaling bits can be 1 or 0.
15-4
15-4
Bit
Bit
3
2
1
0
3
2
1
0
RXSLIPIM
TXSLIPIM
Per Channel Control and Data (Y50 - YAF) Bit Functions
Name
TB(n)
TC(n)
TD(n)
TA(n)
EXZOI
Name
EXZI
#
(0)
(0)
(0)
(0)
Table 108 - Elastic Store and Excessive zero Interrupt Mask Register(Y46) (T1)
#
not used.
Transmit Signaling Bits A for Channel n. Where signaling is enabled, these bits are
transmitted in bit position 8 of the 6th DS1 frame (within the 12 frame superframe structure for
D4 superframes and the 24 frame structure for ESF superframes). This data is obtained from
the CSTi interface but can be overwritten via the Micro port for trunk conditioning applications.
If the MPST bit in the corresponding per timeslot control is not set, this value will be constantly
overwritten by the CSTi stream.
Transmit Signaling Bits B for Channel n. Where signaling is enabled, these bits are
transmitted in bit position 8 of the 12th DS1 frame (within the 12 frame superframe structure
for D4 superframes and the 24 frame structure for ESF superframes).This data is obtained
from the CSTi interface but can be overwritten via the Micro port for trunk conditioning
applications. If the MPST bit in the corresponding per timeslot control is not set, this value will
be constantly overwritten by the CSTi stream.
Transmit Signaling Bits C for Channel n. Where signaling is enabled, these bits are
transmitted in bit position 8 of the 18th DS1 frame within the 24 frame structure for ESF
superframes. In D4 mode these bits are unused. This data is obtained from the CSTi interface
but can be overwritten via the Micro port for trunk conditioning applications. If the MPST bit in
the corresponding per timeslot control is not set, this value will be constantly overwritten by
the CSTi stream.
Transmit Signaling Bits D for Channel n. Where signaling is enabled, these bits are
transmitted in bit position 8 of the 24th DS1 frame within the 24 frame structure for ESF
superframes. In D4 mode these bits are unused.This data is obtained from the CSTi interface
but can be overwritten via the Micro port for trunk conditioning applications. If the MPST bit in
the corresponding per timeslot control is not set, this value will be constantly overwritten by
the CSTi stream.
not used.
Excessive Zero Overflow Interrupt. This bit goes high whenever the excessive zero
counter (Y1B) overflows.This bit is reset after a read of Y36 or Y26.
EXcessive Zero Interrupt. This bit goes high whenever the excessive zero counter (Y1B)
is incremeted by one. This bit is reset after a read of Y36 or Y26.
Transmit SLIP Interrupt Mask. When unmasked an interrupt is initiated whenever a
controlled frame slip occurs in the transmit elastic buffer. If 1 - masked, 0 - unmasked.
Receive SLIP Interrupt Mask. When unmasked an interrupt is initiated whenever a
controlled frame slip occurs in the receive elastic buffer. If 1 - masked, 0 - unmasked.
Table 109 - Per Channel Transmit Signaling Y50-Y67 (T1)
Zarlink Semiconductor Inc.
MT9072
Functional Description
142
Functional Description
Data Sheet