mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 26

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
LQFP
109
128
149
129
150
110
29
49
69
89
10
30
50
70
90
9
Pin #
LBGA
R11
N13
D13
R12
N14
D14
J15
J16
R5
R6
E3
K1
P3
E4
K2
P4
RxDLC[0]
RxDLC[1]
RxDLC[2]
RxDLC[3]
RxDLC[4]
RxDLC[5]
RxDLC[6]
RxDLC[7]
RxDL[0]
RxDL[1]
RxDL[2]
RxDL[3]
RxDL[4]
RxDL[5]
RxDL[6]
RxDL[7]
Name
Type
O
O
Receive Data Link. The entire received data stream including framing
bits, after B8ZS/HDB3 decoding, is clocked out of the RxDL pin by the
clock at the EXCLi pin. RxDL data does not pass through the receive
slip buffer. The embedded data link is flagged by RxDLC. Pins
RxDL[0-7] are used for Framers[0-7] respectively.
In T1 mode this is a 1.544 Mbit/s data stream clocked out with the
rising edge of the clock at the EXCLi pin.
In E1 mode this is a 2.048 Mbit/s data stream clocked out with the
falling edge of the clock at the EXCLi pin.
Receive Data Link Clock. This pin outputs a clock that can be used to
clock selected bits from the RxDL data stream into an external device.
The RxDLC pin can also be configured as an enable signal. Pins
RxDLC[0-7] are used for Framers[0-7] respectively.
In T1 mode the FDL (Facility Data Link) bits embedded in the RxDL
data stream can be clocked into an external device with the rising
edge of this 4 kHz clock. The rising edge of the clock is centered on
the S-bit position and it is coincident with the falling edge of the clock
provided to the EXCLi pin. The RxDLC pin can be configured as a
clock or an enable signal with the DLCK bit (Address Y06). See Figure
49.
In T1 IMA (Inverse Mux for ATM) mode the RxDLC pin outputs the
same 1.544 MHz clock that is input to the EXCLi pin. In IMA mode the
DSTo data stream will be synchronous with this 1.544 MHz clock. IMA
mode is selected by setting the IMA bit (Address Y00) to 1. See Figure
39.
In E1 mode the selected data link national bits (timeslot 0, bits 4-8 of
the NFAS (Non-Frame Alignment Signal) frames) can be clocked into
an external device with the rising edge of this clock. The Receive Data
Link clock is a gapped 4, 8, 12, 16 or 20 kHz, clock as programmed by
the Datalink Control Register (Address Y08), derived by gating the
2.048 MHz clock provided to the EXCLi pin. The RxDLC pin can be
configured as a clock or an enable signal with the DLCK bit (Address
Y08). See Figure 68.
In E1 IMA (Inverse Mux for ATM) mode the RxDLC pin provides an
ST-BUS type 4.096 MHz clock derived by doubling the 2.048 MHz
clock provided to the EXCLi pin. In IMA mode the DSTo data stream
will be synchronous with this 4.096 MHz clock. IMA mode is selected
by setting the IMA bit (Address Y00) to 1. See Figure 58.
Zarlink Semiconductor Inc.
MT9072
26
Description (see Notes 1 to 7)
Data Sheet