mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 249

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mt9072av2

Manufacturer Part Number
mt9072av2
Description
Octal T1/e1/j1 Framer
Manufacturer
Zarlink Semiconductor
Datasheet

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19.2
AC Electrical Characteristics - IMA BackplaneTiming
1
2
3
4
5
6
7
CSTo0
CSTi0
C1.5i Clock Width High or Low
Frame Pulse Setup
Frame Pulse Hold
Serial Input Setup
Serial Input Hold
Clock output delay
Serial Output Delay
ST-BUS Bit Cells
8 Mb/s
FPi
(ST-BUS F16i)
Note: In Cas only the lower nibble of the stream is used
Note: The ABCD bits are bit 3 to bit 0 respectively
T1 Mode
CSTo0
CSTo0
ST-BUS Bit Cells
8 Mb/s
FPi
(ST-BUS F16i)
Note: In CCS the complete Byte is used in accordance with CCS Map register Y07. Any 3 CSTi/CSTo channels are
used
Characteristics
Figure 37 - ST-BUS 8.192 Mb/s Functional Timing Diagram for CSTo/CSTi CAS
Figure 38 - ST-BUS 8.192 Mb/s Functional Timing Diagram for CSTo/CSTi CCS
Timeslot 127
Timeslot 127
Bit 0
t
Sym.
C1.5W
Bit 0
t
t
t
t
t
t
SOD
FPS
FPH
SIS
SIH
cod
Zarlink Semiconductor Inc.
Min.
MT9072
295
50
50
30
50
50
20
249
Channel
CCS
Chan 0
CCS
Chan 0
Channel
0
Typ.
324
90
0
Chan 0
Data
Chan 0
Data
Max.
353
125
Channel
Units
Channel
1
ns
ns
ns
ns
ns
ns
ns
Chan 1
Data
Chan 1
Data
1
150 pF load on CSTo and
DSTo
Channel
CCS
Chan 1
CCS
Chan1
Test Conditions
Channel
2
2
Chan 2
Data
Chan 2
Data
Data Sheet
Channel
Channel
3
3

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