mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 134

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

Bit
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
0
PRBSMFOL PRBS Multiframe Counter Overflow Latch. This bit is set when the PRBS multiframe
MFOOFOL Multiframe Out of Frame Counter Overflow Latch. This bit is set if the Multiframe Out of
COFAOL
PRBSOL
MFSYNL
TFSYNL
CRCOL
OOFOL
BPVOL
COFAL
Name
CRCL
FEOL
FBEL
SEFL
LOSL
AISL
Framing Bit Error Counter Overflow Latch. This bit is set when the framing bit
counter(Y17) overflows. This bit is cleared after a read of Y24 or Y34.
CRC-6 Error Counter Overflow Latch. This bit is set if the CRC6 error counter(Y19)
overflows. This bit is cleared after a read of Y24 or Y34.
Out Of Frame Counter Overflow Latch. This bit is set when the OOF counter(Y1A)
overflows. This bit is cleared after a read of Y24 or Y34.
Change of Frame Alignment Counter Overflow Latch. This bit is set when the change
of frame alignment counter (Y1A) overflows. This bit is cleared after a read of Y24 or Y34.
Bipolar Violation Counter Overflow Latch. This bit is set when the bipolar violation
counter(Y18) overflows.This bit is cleared after a read of Y24 or Y34.
Pseudo Random Bit Sequence Error Counter Overflow Latch. This bit is set when the
PRBS error counter(Y15) overflows. This bit is cleared after a read of Y24 or Y34.
counter(Y15) overflows. This bit is cleared after a read of Y24 or Y34.
Frame Counter(Y16) overflows. This bit is cleared after a read of Y24 or Y34.
Terminal Out Of Sync Latch. This bit is set when the terminal frame out of sync condition
is acquired or lost. It is the latched version of the TFSYNC bit(Y10). This bit is cleared after
a read of Y24 or Y34.
Multiframes Out Of Sync Latch. This bit is set when the multiframes out of sync condition
is acquired or lost. It is the latched version of the MFSYNC bit (Y10).This bit is cleared after
a read of Y24 or Y34.
Framing Bit Error Latch. This bit is set when a framing bit error is detected. It is cleared
upon a read. It is the latched version of the Framing Bit Counter (Y17) event. This bit is
cleared after a read of Y24 or Y34.
Change of Frame Alignment Latch. This bit is set when the change of frame alignment
occurs. This is the latched version of the count event to change of frame counter (Y1A).
This bit is cleared after a read of Y24 or Y34.
Severely Errored Frame Latch. This bit is set upon receipt of a line loopback disable
code. This is a latched version of Y10. This bit is cleared after a read of Y24 or Y34.
AIS Latch. This bit is set upon receipt of an AIS. This is a latched version of AIS(Y10).This
bit is cleared after a read of Y24 or Y34.
CRC Error Latched. This bit is set when the receive CRC error occurs. This bit is cleared
after a read of Y24 or Y34.
Digital Loss of Signal. This bit goes high after the detection of 192 or 32 consecutive
zeros. This is the latched version of LOS(Y10). This bit is cleared after a read of Y24 or
Y34.
Table 96 - Receive Sync and Alarm Latch(Y24) (T1)
Zarlink Semiconductor Inc.
MT9072
134
Functional Description
Data Sheet