mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 41

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mt9072av2

Manufacturer Part Number
mt9072av2
Description
Octal T1/e1/j1 Framer
Manufacturer
Zarlink Semiconductor
Datasheet

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The relationship between DSTi/CSTi and the voice channels in 8.192 Mbit/s mode is shown in Table 2 (F01-F7 refer
to the Framer numbers). There are 2 multiplexed streams (DSTi/o0 and CSTi/o0 are used to multiplexed data for
Framers 0 to 3 and DSTi/o4 and CSTi/o4 is used for framers 5 to 7).
When the device is in IMA (Inverse Mux for ATM) mode, the mapping is the S-bit followed by 24 PCM channels.
This relationship is shown in Table 3. Note that the S-bit location in the Table is indicated by the bit number; which
starts from bit 0. Hence the strict definition of ST-BUS channels is not adhered to. As in a T1 interface the data on
the DSTi/o is a bit followed by 24 channels.
When signaling information is written to the MT9072 using ST-BUS control links (as opposed to direct writes by the
microport to the on-board signaling registers), the CSTi channels corresponding to the selected DSTi channel
streams are used to transmit the signaling bits. Since the maximum number of signaling bits associated with any
channel is 4 (in the case of ABCD), only half a CSTi (bits 3 to 0) channel is required for sourcing the signaling bits.
Bit A is bit 3 from the CSTi stream, Bit B is 2, Bit C is 1 and Bit D is 0. Unused channels and unused bits are tristate.
In T1 transparent mode, the DSTi data is transparently sent to the PCM24 channels. In transparent mode the data
on the DSTi streams will appear unaltered on the PCM24 links and data received on the PCM24 link will pass
unaltered to the DSTo streams. No signaling insertion or extraction is done in transparent mode. If the TxSYNC
control bit (address Y00) is 1 then the transmit S-bit is overwritten by channel 31 bit 0 in the 2.048 Mbit/s ST-BUS
mode. In the 8.192 Mbit/s ST-BUS mode the S-bits from channels 124, 125, 126, 127 respectively are used to
override the transmit S-bit positions for Framers 0 to 3 or 4 to 7 respectively. If T1 Transparent mode and IMA mode
are both selected then the S-bit and channel bits are transparently mapped as shown in Table 3.
PCM24 Channels
ST-BUS Channels
(DSTi/o and CSTi/o)
PCM24 Channels
ST-BUS Channels
(DSTi/o and CSTi/o)
PCM24 Channels
ST-BUS
Chan(DSTi/o
and CSTi/o)
PCM24 Channels
ST-BUS
Chan(DSTi/o
and CSTi/o)
Table 2 - ST-BUS Channel vs. PCM24 Channel Relationship for 8.192 Mbit/s DST/CST Streams (T1)
Table 1 - ST-BUS vs. PCM24 Channel Relationship for 2.048 Mbit/s DST/CST Streams (T1)
F2/6
F3/7
F2/6
F3/7
F0/4
F1/5
F0/4
F1/5
17
64
65
66
67
17
16
1
0
1
2
3
1
0
18
68
69
70
71
18
17
2
4
5
6
7
2
1
10
11
19
72
73
74
75
19
18
3
8
9
3
2
12
13
14
15
20
76
77
78
79
20
19
4
4
3
Zarlink Semiconductor Inc.
16
17
18
19
21
80
81
82
83
21
20
5
5
4
MT9072
20
21
22
23
22
84
85
86
87
6
22
21
6
5
41
24
25
26
27
23
88
89
90
91
7
23
22
7
6
28
29
30
31
24
92
93
94
95
8
24
23
8
7
S-bit
24
124
125
126
127
9
7
32
33
34
35
x
-
9
10
25
9
x
-
10
36
37
38
39
-
10
26
11
x
-
40
41
42
43
11
-
12
27
11
x
-
12
44
45
46
47
-
13
12
28
x
-
13
48
49
50
51
-
14
13
29
x
-
14
52
53
54
55
-
Data Sheet
15
14
30
x
-
15
56
57
58
59
-
S-bit
16
15
31
16
60
61
62
63
-

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