mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 217

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

15-11 CHANNUM
10-8
Bit
15
14
13
12
7-6
4-2
Bit
5
1
0
Name
F3HM
F3RM
F3EM
F3SM
STBUFEN
CONTSIN
(0)
(0)
(0)
(0)
STRNUM
(00000)
(00000)
FNUM
CHUP
Name
(000)
(0)
(0)
(0)
#
Framer 3 HDLC Mask. This is the mask bit for the F3HVS status bit in the Interrupt Vector
Register(address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 3 Elastic Mask. This is the mask bit for the F3EVS status bit in the Interrupt Vector
Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 3 Rx Line Mask. This is the mask bit for the F3RVS status bit in the Interrupt Vector
Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 3 Sync and Overflow Mask. This is the mask bit for the F3SVS status bit in the Interrupt
Vector Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit
will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Table 196 - Interrupt Vector 1 Mask Register (R/W Address 902) (E1)
Channel Number. These 5 bits determine the channel that is used for updating of the
ST-BUS Analyzer buffer.
not used.
Stream Number. These 5 bits determine the streams that will be used as the source data
for the ST-BUS Analyzer buffer.
00: Dsti
01: DSTo
10: Csti
11: Csto
ST-BUS Analyser Buffer Enable. Setting this bit enables the ST-BUS Analyser Buffer
update. When the user reads the buffer(920-93F), this bit must be 0. Any reads of the buffer
while this bit is set does not ensure correct data being read.
Framer Number. 0 to 7.
Channel Update. If 0 the update of the memory is at frame rate for a given channel. The
channel selected for update is provided by the ChanNum bits of this register. If set the
complete frame(channels 0 to 32) are updated to the buffer.
Continuous Single. If set to 1 the ST-BUS Analyzer buffer is updated continuously. If set to
zero the buffer is updated once and stopped. An optional interrupt can be generated once
the buffer is full.
Table 195 - Global Control1 Register (R/W Address 901) (E1)
Zarlink Semiconductor Inc.
MT9072
Functional Description
217
Functional Description
Data Sheet