mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 32

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
LQFP
137
157
117
37
57
77
18
98
Pin #
LBGA
G15
B13
T16
L13
M1
N9
G4
T3
CSTo[1]
CSTo[2]
CSTo[3]
CSTo[5]
CSTo[6]
CSTo[7]
Name
CKi[0]
CKi[4]
Type
OH Control ST-BUS. In 2.048 Mbit/s ST-BUS mode this pin is the
I
signaling output for the receive side of the framer. The CSTo data
stream is clocked out of the framer by the clock input to pin CKi. This
pin has no function in 8.192 Mbit/s ST-BUS mode or IMA mode. Pins
CSTo[0-7] are used by Framers[0-7] respectively.
In T1 robbed bit signaling mode, the first 24 ST-BUS channels contain
(XXXXABCD) signaling nibbles received for their respective DS0s.
The least significant nibbles (bits 3-0) are valid and the most
significant nibbles of each channel are in a high impedance state. The
CSTo pin is enabled if the CSToEN control bit (Address YF1) is set to
1.
In T1 CCS (Common Channel Signaling) mode, the CSTo pin can be
connected to the input of an external multi-channel HDLC. Any one of
the framer’s receive timeslots be programmed to output their received
data on the CSTo pin on any one of the first 24 ST-BUS channels.
CSTo is in a high impedance state during unused channels. See the
descriptions of the CSIGEN control bit (Address Y04) and the
Common Channel Signaling Map Register (Address Y0B). The CSTo
pin is enabled if the CSToEN control bit (Address YF1) is set to 1.
In E1 CAS (Channel Associated Signaling) mode, the 32 ST-BUS
channels contain (XXXXABCD) signaling nibbles received for their
respective timeslots. The least significant nibbles (bits 3-0) are valid
and the most significant nibbles of each channel are in a high
impedance state. See Table 26. The CSTo pin is enabled if the CSToE
control bit (Address Y02) is set to 1.
In E1 CCS (Common Channel Signaling) mode, the CSTo pin can be
connected to the input of an external multi-channel HDLC. The
framer’s receive timeslots 15, 16 and 31 can each be programmed to
output their received data on the CSTo pin during any one of the 32
ST-BUS channels. CSTo is in a high impedance state during unused
channels. See the descriptions of the CSIG control bit (Address Y03)
and the TS15E, TS16E and TS31E bits (Address Y06) and see
Table 29. The CSTo pin is enabled if the CSToE control bit (Address
Y02) is set to 1.
System Clock. In 2.048 Mbit/s ST-BUS mode and 8.192 Mbit/s
ST-BUS mode this pin accepts the clock that is used to time the
transmit side and the receive side of the framer. The CKi clock rate is
determined by control bits at (Address 900)
In 2.048 Mbit/s ST-BUS mode and in IMA mode, operation is the same
as that described for pins CKi[1-3].
In 8.192 Mbit/s ST-BUS mode this pin accepts the ST-BUS type
16.384 MHz clock that is used to time the 8.192 Mbit/s data appearing
at pins DSTi, CSTi, DSTo and CSTo. In this mode pin CKi[0] is used by
framers[0-3] and pin CKi[4] is used by framers[4-7]. See Figure 36.
8.192 Mbit/s operation is not available in IMA mode.
Zarlink Semiconductor Inc.
MT9072
32
Description (see Notes 1 to 7)
Data Sheet