mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 24

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

Pin Description
81,101,121,
82,102,122,
1,21,41,61,
2,22,42,62,
142,162,18
141,161,
LQFP
179
103
123
143
104
124
144
105
125
145
23
43
63
83
24
44
64
84
25
45
65
85
0
3
4
5
Pin #
M7,M8,M9,
K5,L5,G12,
H12J12,K1
E7,E8,E9,
G5,H5,J5,
M10,M11
E10,E11,
LBGA
2,L12
R15
K13
F15
P10
R16
K14
F16
P13
K15
E13
P11
D1
H3
N1
N7
D2
H4
N2
N8
D3
N3
P9
P5
J1
EXCLi(0)
EXCLi(1)
EXCLi(2)
EXCLi(3)
EXCLi(4)
EXCLi(5)
EXCLi(6)
EXCLi(7)
RPOS[0]
RPOS[1]
RPOS[2]
RPOS[3]
RPOS[4]
RPOS[5]
RPOS[6]
RPOS[7]
RNEG[0]
RNEG[1]
RNEG[2]
RNEG[3]
RNEG[4]
RNEG[5]
RNEG[6]
RNEG[7]
Name
V
V
DD
SS
Type
P
P
I
I
I
Ground. 0V
Supply Voltage. +3.3 V
Receive Positive. This pin is an input for the receive side of the
framer; it typically interfaces to an LIU. If used by itself it can accept
single rail NRZ (Non Return to Zero) data. If RPOS is used in
conjunction with RNEG it can accept dual rail NRZ data or dual rail RZ
(Return to Zero) data. The clock at the EXCLi pin is used to clock data
into the RPOS pin. Pins RPOS[0-7] are used for Framers[0-7]
respectively.
In T1 mode, transmit line codes are selected with control bits:
RZCS1-0, RXB8ZS, RZNRZ and UNIBI (Address Y01). T1 mode is
selected if the T1E0 bit (Address 900) is 1.
In E1 mode, line codes are selected with control bits: COD0-1 and
RHDB3 at (Address Y02). E1 mode is selected if the T1E0 bit
(Address 900) is 0.
Receive Negative. This pin is an input for the receive side of the
framer; it typically interfaces to an LIU. RNEG is used in conjunction
with RPOS to accept dual rail NRZ (Non Return to Zero) data or dual
rail RZ (Return to Zero) data. The clock at the EXCLi pin is used to
clock data into the RNEG pin. Pins RNEG[0-7] are used for
Framers[0-7] respectively.
In T1 mode, receive line codes are selected with control bits:
RZCS1-0, RXB8ZS, RZNRZ and UNIBI at (Address Y01). T1 mode is
selected if the T1E0 bit (Address 900) is 1.
In E1 mode, line codes are selected with control bits: COD0-1 and
RHDB3 at (Address Y02). E1 mode is selected if the T1E0 bit
(Address 900) is 0.
1.544/2.048 MHz Extracted Clock. The rising edge of the clock
applied at this input is used to clock RZ data into the receive side of
the framer on pins RPOS and RNEG. If RPOS/RNEG are configured
for NRZ input then either a rising or falling edge on the EXCLi clock
can be selected to clock RPOS/RNEG data. Pins EXCLi[0-7] are used
for Framers[0-7] respectively.
In T1 mode, this pin accepts a 1.544 MHz extracted clock. An active
rising or falling edge is selected with the CLKE bit (Address Y01). See
Figure 53.
In E1 mode, this pin accepts a 2.048 MHz extracted clock. An active
rising or falling edge is selected with the CLKE bit (Address Y02). See
Figure 73.
Zarlink Semiconductor Inc.
MT9072
24
DC
.
Description (see Notes 1 to 7)
DC
nominal.
Data Sheet