mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 207

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

Table 182 - Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Mask Register (Address Y44)
Table 183 - Counter (Counter Indication and Counter Overflow) Interrupt Mask Register (Address Y45)
Bit
Bit
15
14
13
12
11
10
2
1
0
9
MSYNCM
CSYNCM
BSYNCM
FEOM
BEOM
CEOM
SLOM
Name
Name
FEIM
BEIM
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
#
Receive CRC-4 Synchronization Mask. This is the mask bit for the CSYNCI interrupt status
bit in the Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register
(address Y34). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this
mask bit is zero, the corresponding interrupt bit will function normally.
Receive Multiframe Alignment Mask. This is the mask bit for the MSYNCI interrupt status
bit in the Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register
(address Y34). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this
mask bit is zero, the corresponding interrupt bit will function normally.
Receive Basic Frame Alignment Mask. This is the mask bit for the BSYNCI interrupt status
bit in the Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register
(address Y34). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this
mask bit is zero, the corresponding interrupt bit will function normally.
not used.
Loss of Sync Counter Overflow Mask. This is the mask bit for the SLOI interrupt status bit
in the Counter (Counter Indication and Counter Overflow) Interrupt Status Register (address
Y35). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit
is zero, the corresponding interrupt bit will function normally.
Frame Alignment Signal (FAS) Error Counter Overflow Mask. This is the mask bit for the
FEOI interrupt status bit in the Counter (Counter Indication and Counter Overflow) Interrupt
Status Register (address Y35). If this mask bit is one, the corresponding interrupt bit will
remain inactive. If this mask bit is zero, the corresponding interrupt bit will function normally.
Frame Alignment Signal (FAS) Error Counter Indication Mask. This is the mask bit for the
FEII interrupt status bit in the Counter (Counter Indication and Counter Overflow) Interrupt
Status Register (address Y35). If this mask bit is one, the corresponding interrupt bit will
remain inactive. If this mask bit is zero, the corresponding interrupt bit will function normally.
Frame Alignment Signal (FAS) Bit Error Counter Overflow Mask. This is the mask bit for
the BEOI interrupt status bit in the Counter (Counter Indication and Counter Overflow)
Interrupt Status Register (address Y35). If this mask bit is one, the corresponding interrupt bit
will remain inactive. If this mask bit is zero, the corresponding interrupt bit will function
normally.
Frame Alignment Signal (FAS) Bit Error Counter Indication Mask. This is the mask bit for
the BEII interrupt status bit in the Counter (Counter Indication and Counter Overflow) Interrupt
Status Register (address Y35). If this mask bit is one, the corresponding interrupt bit will
remain inactive. If this mask bit is zero, the corresponding interrupt bit will function normally.
CRC-4 Error Counter Overflow Mask. This is the mask bit for the CEOI interrupt status bit in
the Counter (Counter Indication and Counter Overflow) Interrupt Status Register (address
Y35). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit
is zero, the corresponding interrupt bit will function normally.
Zarlink Semiconductor Inc.
MT9072
Functional Description
Functional Description
(E1)
(E1)
207
Data Sheet