mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 69

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

8.2.3
The CSIG control bit (register address Y03) must be set to one for Common Channel signaling (CCS) operation.
CCS on the transmit PCM30 link (bit positions one to eight of timeslots 15, 16 and/or 31 of every frame) may be
sourced from the ST-BUS DSTi stream or from the ST-BUS CSTi stream. If the TS15E, TS16E & TS31E control bits
(register address Y06) are zero, the transmit data will be sourced from the ST-BUS DSTi stream timeslots 15, 16
and 31, if these bits are one, then the signaling data will be sourced from the ST-BUS CSTi stream. Note that any
combination of the TS15E, TS16E & TS31E control bits (register address Y06) may be enabled. The CSTi source
timeslots for the PCM30 timeslot 15, 16 and 31, are determined respectively by the 15C4-15C0, 16C4-31C0 and
31C4-31C0 (register address Y07) programming bits. Table 27 shows the detailed bit mapping of CSTi timeslots to
transmit PCM30 frames. Table 28 shows the detailed bit mapping of DSTi timeslots to transmit PCM30 frames.
Note 1. For 2.048 Mbit/s operation, m=1 and n=0.
Note 2. For 8.192 Mbit/s operation, m=4 and n =0,1,2,3 where n corresponds to the framer number (i.e., n=0=framer 0... n=3= framer
3)
Note 3. For these functions to be valid, CCS mode must be selected (CSIG=1 register address Y03) and CSTi ST-BUS mode must be
selected (TS15E=1, TS16E=1 & TS31E=1 register address Y06) and the preferred source CSTi timeslot should be selected (15C4-0,
16C4-0 & 31C4-0 register address Y07).
Note 1. For 2.048 Mbit/s operation, m=1 and n=0.
Note 2. For 8.192 Mbit/s operation, m=4 and n =0,1,2,3 where n corresponds to the framer number (i.e., n=0=framer 0... n=3= framer 3).
Note 3. For these functions to be valid, CCS mode must be selected (CSIG=1 register address Y03), and DSTi ST-BUS mode must be selected
(TS15E=0, TS16E=0 & TS31E=0 register address Y06).
CRC-4
Frame
CRC-4
Frame
all
all
all
all
all
all
E1 Common Channel Signaling (CCS) Transmit from ST-BUS CSTi and DSTi to PCM30
Table 27 - Transmit PCM30 CCS from ST-BUS 2.048 Mbit/s or 8.192 Mbit/s CSTi (E1)
Table 28 - Transmit PCM30 CCS from ST-BUS 2.048 Mbit/s or 8.192 Mbit/s DSTi (E1)
n + m(15)
n + m(16)
n + m(31)
Timeslot
n + m(0 to 31)
n + m(0 to 31)
n + m(0 to 31)
Any one of 32
Any one of 32
Any one of 32
Timeslot
ST-BUS DSTi
ST-BUS CSTi
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
Data Bits (B7-B0)
Data Bits (B7-B0)
Zarlink Semiconductor Inc.
MT9072
69
Timeslot
15
16
31
Timeslot
15
16
31
CRC-4
Frame
CRC-4
Frame
all
all
all
all
all
all
PCM30 Transmit
PCM30 Transmit
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
Data Bits (B1-B8)
Data Bits (B1-B8)
Data Sheet