mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 93

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

14.2
Extensive maintenance and alarm generation and detection functions are provided on the MT9072. The following
table groups the registers for control and monitor of these functions.
14.2.1
Six types of error conditions can be inserted into the transmit PCM30 data stream through register control bits
located at address Y01. These error events include the bipolar violation errors (BVE), CRC-4 errors (CRCE), FAS
errors (FASE), NFAS errors (NFSE), payload (PERR) and a loss of signal error (LOSE). The LOSE function
overrides the HDB3 encoding function (no BPV are added). Also included are E1 and E2 error bit insertion on
frames 13 and 15. See the bit descriptions (control register address Y01) for additional details.
14.2.2
There are 32 per timeslot control registers occupying a total of 32 unique addresses (Y90-YAF). Each register
controls a matching timeslot on the 32 transmit channels (onto the line) and the equivalent channel data on the
receive (DSTo) data. For example, register address Y91 of the first per timeslot control register contains program
control for transmit timeslot 1 and DSTo channel 1.
14.2.3
Any channel or combination of channels may be looped from transmit (sourced from DSTi) to receive (output on
DSTo) ST-BUS channels. When bit 4 (LTSL) in the Per Timeslot Control Word is set the data from the equivalent
transmit timeslot is looped back onto the equivalent receive channel.
Any channel or combination of channels may be looped from receive (sourced from the line data) to transmit
(output onto the line) channels. When bit 5 (RTSL) in the Per Timeslot Control Word is set the data from the
equivalent receive timeslot is looped back onto the equivalent transmit channel.
Register
Address
Y00
Y01
Y05
Y10
Y11
Y12
Y24
Y34
Y44
E1 Maintenance and Alarms
E1 Error Insertion
E1 Per Timeslot Control
E1 Per Timeslot Looping
Alarm and Framing Control Register The TAIS and E bit errors and RAI can be set by this register.
Test Error and Loopback Control
Register
CAS Control and Data Register
Synchronization and CRC-4
Remote Status
CRC-4 Timer and CRC-4 Local
Status
Alarms and MAS Status
Sync, CRC-4 remote alarm, MAS
Latched Status Register
Sync, CRC-4 Remote Alarm, MAS
Interrupt status register
Sync, CRC-4 Remote Alarm, MAS
Interrupt register mask
Table 47 - Registers Related to Maintenance and Alarms (E1)
Register
Zarlink Semiconductor Inc.
BPVE, CRCE,FASE, NFSE and E bit errors can be inserted.
The Y bit can be used to send Remote Multiframe Alarm signal.
The bits of this register provide good receiver error status.
The CRC-4 errors are registered in Y11.
This register provides AIS, RAI, LOSS status bits.
Latched version of receive CRC errors and synchronization loss
are available.
This register provides bits for interrupt generation for Y24 CRC
errors and synchronization loss functions.
This register provides bits for interrupt mask register for Y34.
MT9072
93
Description
Data Sheet