mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 135

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D4YALML
SECYELL
ESFYELL
T1DMYL
D4Y48L
BOMML
PRBSL
CASRL
LLDDL
1SECL
2SECL
LLEDL
BOML
Name
BPVL
PDVL
#
D4 Yellow Alarm Latch. This bit is set if a D4 yellow alarm is detected within a 600
millisecond integration period. This bit is cleared after a read of Y25 or Y35.
D4 Yellow Alarm (48 milliseconds) Latch. This bit is set if a D4 yellow alarm is detected
within a 48 millisecond integration period. This bit is cleared after a read of Y25 or Y35.
Secondary D4 Yellow Alarm Latch. This bit is set if Secondary yellow alarm D4 (S bit in
12 th frame) is detected. It is cleared after a read.This bit is cleared after a read of Y25 or
Y35.
ESF Yellow Alarm Latch. This bit is set upon receipt of a ESF yellow alarm. This bit is
cleared after a read of Y25 or Y35.
T1DM Yellow Alarm Latched. If this bit is 1 a T1DM yellow alarm is received on bit 2 of
24th timeslot. This bit is cleared after a read of Y25 or Y35.
not used.
Bipolar Violation Latch. This bit is set when a bipolar violation occurs. This bit is cleared
after a read of Y25 or Y35.
PRBS Latch. This bit is set when a PRBS error has occured.This bit is cleared after a
read of Y25 or Y35.
Pulse Density Violation Latch. This bit is set when the receive PDV is detected.This bit
is cleared after a read of Y25 or Y35.
Line Loopback Enable Detect Latch. This bit is set upon receipt of a line loopback
enable code. It is cleared after a read. This is a latched version of LLED(Y10).This bit is
cleared after a read of Y25 or Y35.
Line Loopback Disable Detect Latch. This bit is set upon receipt of a line loopback
disable code. It is cleared after a read. This is a latched version of LLDD(Y10).This bit is
cleared after a read of Y25 or Y35.
Bit Oriented Message Latch. This bit is set if a bit oriented message has been received.
It is cleared upon a read.This bit is cleared after a read of Y25 or Y35.
Bit Oriented Message Match Latch. This bit is set if the bit oriented message received
matches the value of the Bit Oriented Match register.This bit is cleared after a read of Y25
or Y35.
Channel Associated signaling Received Latch. This bit is set if the received CAS has
changed on any of the 24 channels.This bit is cleared after a read of Y25 or Y35.
1 Second Latch. This bit is set if the one second timer expires. This bit is cleared after a
read of Y25 or Y35.
2 Second Latch. This bit is set if the two second timer expires. This bit is cleared after a
read of Y25 or Y35.
Table 97 - Receive Line Status and Timer Latch(Y25) (T1)
Zarlink Semiconductor Inc.
MT9072
135
Functional Description
Data Sheet