mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 81

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

10.1.5.2
The TAIS pin allows all eight framers of the MT9072 to transmit an all ones signal (AIS) at the TPOS and TNEG
output pins from the point of power-up, without the need to write any control registers. During this time the IRQ pin
is in a high impedance state. After the interface has been initialized normal operation can take place by making
TAIS high.
10.1.5.3
Five signals (TDI, TDO, TMS, TCK & TRST) make up the Test Access Port (TAP) of the IEEE 1149.1-1990
Standard Test Port and Boundary-Scan Architecture. The TAP provides access to test support functions built into
the MT9072. The TAP is also referred to as a JTAG (Joint Test Action Group) port. See the JTAG section for
additional details.
10.1.6
Dedicated data link pins are included which provide the user the option of bypassing the receive elastic buffer and
accessing timeslot 0 data link (DL) data with an external controller. The MT9072 provides numerous additional
methods for accessing the DL, refer to the DL sections for details.
Transmit MFAS (CAS)
ABCD Bit Debounce
Per Timeslot Control
Transmit non-FAS
CRC Interworking
All Other Control
Counter Latches
Error Insertion
Transmit FAS
Data Link Pin
RxMF Output
Loopbacks
Function
Interrupts
Registers
Signaling
Counters
Buffer
Data Link (DL) Interface (RxDL, RxDLC, TxDL, TxDLC Pins)
Mode
Transmit AIS Operation (TAIS Pin)
IEEE 1149.1-1990 Test Access Port (TAP)
CAS ST-BUS Source
signaling Multiframe
All locations cleared
All locations cleared
All Unmasked
Deactivated
1/S
Deactivated
Deactivated
Deactivated
Termination
C
Suspended
00001111
Activated
Cleared
Cleared
n
Status
0011011
n
1111111
Table 37 - Reset Status (E1)
Zarlink Semiconductor Inc.
MT9072
81
Sa4SS1-0,Sa5SS1-0,Sa6SS1-0,Sa
E1, E2, BPVE,CRCE,FASE,
DLBK,RLBK,SLBK,PLBK=0
NFSE,LOSE,PERR=0
7SS1-0,Sa8SS1-0=0
RxTRS=0, TxTRS=0
RTSL(n), LTSL(n)=0
ALL MASK BITS =0
SPND=0, INTA=0
TMA1,2,3,4=0
X1,Y,X2,X3=1
Control Bits
ALL BITS =0
ALL BITS =0
ALL BITS =0
ALL BITS =0
CASS(n)=0
DBNCE=0
MFSEL=0
CSYN=0
AUTC=0
CSIG=0
Register Address
All Other Control
Y90-YAF
Y50-Y6F
Y15-Y1A
Y28-Y2B
Y90-YAF
Y40-Y43
Data Sheet
Y03
Y01
Y00
Y03
Y03
Y03
Y05
Y05
Y08
Y00
Y03
Y05
Y02
Y02
Y01