mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 79

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

10.1.4
Dedicated multiframe boundary pins are included which provide the user the option of setting the multiframe
boundaries and identifying the multiframe boundaries with an external device. Refer to the RxMF and TxMF pin
descriptions.
10.1.5
10.1.5.1
The MT9072 can be reset using the hardware RESET pin or the software reset bits: RST (register address YF1)
and RSTC (address 900). The RST bit resets a particular framer and the RSTC bit is a global software reset bit.
On initial power up, a hard reset must be done using the RESET pin. A valid reset condition requires both of these
inputs to be held low for a minimum of 100 ns. These inputs should be set to zero during initial power up, then set to
one.
After initial power up, the MT9072 can be reset using the hardware RESET pin or the software reset bit RSTC
(register address 900). When the device emerges from its reset state, it will begin to function in T1 mode and the
control registers will be initialized as described in Table 36. Clearing the T1E0 bit in register 900 to place the
MT9072 in E1 mode will cause another internal reset and the control registers will be initialized to their E1 defaults
as described in Table 37. In addition, individual framers may be reset with the software reset bit RST. Using the
RST will reset the individual framer to its default E1 or T1 setting. RST will not affect the common control register
(9xx). All reset operations take 1 full frame (125 us) to complete. Refer to the RESET pin description, RSTC and
RST bit descriptions for additional details.
Line Coding and
Transmit Alarms All sending alarms are deactivated.
Framing Mode
Register
Address
Function
Interface
Y00
Y06
Signaling Multiframe Boundary (RxMF, TxMF Pins)
Control Pins
Reset Operation (RESET Pin, RST Bit and RSTC Bit)
Framing Mode Select
HDLC & Datalink Control
Mode D4,Reframe criteria is set for 2
bits errors in 4 bits,Fs bit is not
included in the synchronization
criteria, S-bit not included in CRC
calculation. The elastic stores are not
bypassed.
The T1 interfaces are set to NRZ,
Bipolar,and Rising edge of clocks for
output and falling for input line
clocks.TxB8ZS and RxB8ZS and
Transmit PDV enforcer is turned off.
Register
Table 35 - Registers Related to IMA Mode
Status
Table 36 - Reset Status (T1)
Zarlink Semiconductor Inc.
Setting the IMA bit will cause the framer to enter IMA mode.
E1.5CK bit must be set to provide a 1.544 MHz clock on
RXDLC.
MT9072
79
RELBY,TELBY,TRANSP,T1DM,ESF,SLC
96,CXC,RS10,FSI,ReFR,MFReFR,JTS,T
XSYNC =0
RZCS1:0,TZCS2:0TPDV,TXB8ZS,RXB8
ZS,ADSEQ,RZNRZ,UNIBI,CLKE = 0
TESFYEL,TXSECY,TD4YEL,TAIS,
#,T1DMY,D4SECY,SO = 14
Control Bits Reset Value
Description
Data Sheet
Register
Address
Y00
Y01
Y02