mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 131

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

15-12
15-7
5-4
3-2
1-0
Bit
7-0
Bit
10
11
6
9
8
RXSTAT1-0 Receive FiFO Status:
TXSTAT1-0 Transmit FiFO Status:
TBP7-0
Name
RQ9-8
RXclk
TXclk
Vaddr
Name
Vcrc
IDC
#
Table 91 - Transmit Byte Counter Position and HDLC Test Status(Y1C) (T1)
#
not used.
This bit represents the receiver clock generated after the RXEN control bit, but before
zero deletion is considered.
This bit represents the transmit clock generated after the TXEN control bit, but before zero
insertion is considered.
This is the CRC recognition status bit for the receiver. Data is clocked into the register and
then this bit is monitored to see if comparison was successful (bit will be high).
This is the address recognition status bit for the receiver. Data is clocked into the Address
Recognition Register and then this bit is monitored to see if comparison was successful
(bit will be high).
Transmit Byte Counter Position. These 7 bits provide the position of the Transmit HDLC
Byte Counter register (YF6). The counter is decremented as a byte of data is sent through
the Transmit FIFO.
When this register reaches the count of one, the next write to the Tx FIFO will be tagged
as an end of packet byte. The counter decrements at the end of the write to the Tx FIFO.
If the Cycle bit of YF2 is set high, the counter will cycle through the programmed value
continuously.
not used.
Idle Channel State.Is set to a 1 when an idle Channel state (15 or more ones) has been
detected at the receiver. This is an asynchronous event. On power reset, this may be 1 if
the clock (RXC) was not operating. Status becomes valid after the first 15 bits or the first
zero is received.
RQ9-8Byte Status bits from RX FIFO. These bits determine the status of the byte to be
read from RX FIFO as follows:
00 Packet Byte
01 First Byte
10 Last byte of good packet
11 Last byte of bad packet
00 Transmit FIFO is full.
01 The number of bytes in the transmit FIFO has reached or exceeded the 16 bytes
threshold
10 Transmit FIFO is empty
11 The number of bytes in the TX FIFO is less than the 16 byte threshold.
00 Receive FIFO is empty.
01 The number of bytes in the Receive FIFO are less than the 16 bytes
10 Receive FIFO is full
11 The number of bytes in the Receive FIFO is greater than or equal to the 16 byte
threshold.
Table 92 - HDLC Status Word(Y1D) (T1)
Zarlink Semiconductor Inc.
MT9072
131
Functional Description
Functional Description
Data Sheet