mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 59

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

7.2
Table 12 shows the contents of the transmit and receive Frame Alignment Signals (FAS) and Non-frame Alignment
Signals (NFAS) of timeslot zero of a PCM30 signal. Even numbered frames (CRC Frame # 0, 2, 4,...) are FASs and
odd numbered frames (CRC Frame # 1, 3, 5,...) are NFASs. The bits of each channel are numbered 1 to 8, with bit
1 being the most significant and bit 8 the least significant. The Data Link (DL) bits, also referred to as National bits,
are the Sa4, Sa5, Sa6, Sa7 and Sa8 bits of the PCM30 timeslot zero NFAS frames. Any number and combination
of these bits may be used for the transport of maintenance and performance monitoring information across the
PCM30 link. The DataLink in controlled by the address Y06 and Y08.
The received Data Link bits are always sent to the DataLink Pins and the National bit buffers(YC0-YC4).
The Data Link (DL) bits (S
following four ways:
•
•
•
•
Note: that the user can source different Sa bits from a combination of the above 4 methods. For instance the Sa
bit could be sourced from the External Serial Port and Sa
to YB4).
The registers related to the configuration control and status of the data link are shown in Table 17.
YC0-YC4 Receive national bit
YB0-YB4 Transmit National Bits
Register
Address
External serial port pins. Hence the user can use pins (TxDL and TxDLC) for transmit data link access and
RxDL and RXDLC for receive data link access
Receive 5 bit register (RNU4-8 address YC0-YC4).
ST-BUS access Transmit ST-BUS (DSTi timeslot 0) enabled by transparent mode
On board HDLC for Timeslot 0
Micro port access which would use Transmit 5 bit register (TNU4-8 address YB0 to YB4). For the receiver
Y00
Y06
Y08
Y13
Y26
Y36
Y46
E1 Data Link (DL) Operation
Alarm and Framing Control
Register
HDLC and CCS ST-BUS
control register
Data Link Control Register
NFAS and FAS status
CAS, National, CRC-4
Latched Status
CAS, National, CRC-4
Interrupt Status
CAS, National, CRC-4
Interrupt Mask
Table 17 - Data Link and Sa Bits Configuration and Status Registers (E1)
Register
a4
~S
a8
) of the PCM30 timeslot zero NFAS frames can be accessed by the MT9072 in the
The Data Link is not supported in the IMA mode.
The bit HPSEL has to be 0 if the internal HDLC is to be used for the
Data Link.
This register determines the source of the Sa bits which can be micro
port,HDLC, data link pins or ST-BUS. This register is also used to
control the data link pins Txdl and Rxdl.
The national use bits RNU can be read from this status register.
The Sa bit latched values can be read from this register, SA5VL,
SA6NL etc.
The Sa bit interrupt values can be read from this register, SA5VI,
SA6NI etc.
These are the mask bits for Y36.
Transmit national bits used for sending
Sa bits(SA4 to SA8).
Receive National bits(SA4 to SA8)
Zarlink Semiconductor Inc.
MT9072
59
5
to Sa
8
from the micro port register (TNU5-8 address YB1
Description
Data Sheet
4