mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 139

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

15-9
Bit
Bit
15
14
13
12
8
7
6
5
4
3
2
1
0
TXUNDERIM
RXOVFLIM
COFAOIM
EOPDIM
EOPRIM
TEOPIM
RXFFIM
CRCOIM
OOFOIM
TXFLIM
FEOIM
Name
GAIM
FAIM
Name
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
#
Table 106 - Receive and Sync Interrupt Mask Register(Y44) (T1)
not used.
Go Ahead Interrupt Mask. When unmasked an interrupt is generated when go-ahead
pattern (01111111) was detected by the HDLC receiver.
End of Packet Data Interrupt Mask. When unmasked an interrupt is initiated when an end
of packet (EOP) byte was written into the RX FIFO by the HDLC receiver.
Transmit End of Packet Interrupt Mask. When unmasked an interrupt is initiated when
the transmitter has finished sending the closing flag of a packet or after a packet has been
aborted.
End of Packet Received Interrupt Mask. When unmasked an interrupt is initiated when
the byte about to be read from the RX FIFO is the last byte of the packet. An interrupt is
also initiated if the Rx FIFO is read and there is no data in it.
Transmit Fifo Low Interrupt Mask. When unmasked an interrupt is initiated when the Tx
FIFO is emptied below the selected low threshold level.
Frame Abort: Transmit Interrupt Mask. When unmasked an interrupt is initiated this bit
(FA) is set when a frame abort is received during packet reception. It must be received after
a minimum number of bits have been received (26) otherwise it is ignored.
Transmit Fifo Underrun Interrupt Mask. When unmasked an interrupt is initiated for TX
FIFO underrun indication.
Receive Fifo full Threshold interrupt Mask. When unmasked an interrupt is initiated
whenever the Rx FIFO is filled above the 16 byte threshold level.
Receive Fifo Overflow Interrupt Mask. When unmasked an interrupt is initiated
whenever the 32 byte RX FIFO overflowed (i.e., an attempt to write to a 32 byte full RX
FIFO).
Framing Bit Error Counter Overflow Interrupt Mask. When unmasked an interrupt is
initiated whenever the framing bit error counter changes from FFH to 00H. 1 -masked, 0 -
unmasked.
CRC-6 Error Counter Overflow Interrupt Mask. When unmasked an interrupt is initiated
whenever the CRC-6 error counter changes from FFH to 00H. 1 - masked, 0 - unmasked.
Out Of Frame Counter Overflow Interrupt Mask. When unmasked an interrupt is
initiated whenever the out of frame counter changes state from changes from FFH to 00H.
1 - masked, 0 - unmasked.
Change of Frame Alignment Counter Overflow Interrupt Mask. When unmasked an
interrupt is initiated whenever the change of frame alignment counter changes from FFH to
00H. 1 - masked, 0 - unmasked.
Table 105 - HDLC Interrupt Mask Register(Y43) (T1)
Zarlink Semiconductor Inc.
MT9072
139
Functional Description
Functional Description
Data Sheet