mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 188

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mt9072av2

Manufacturer Part Number
mt9072av2
Description
Octal T1/e1/j1 Framer
Manufacturer
Zarlink Semiconductor
Datasheet

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Bit
15
14
13
12
10
11
Bit
15
14
13
12
10
9
8
7
6
5
4
3
2
1
0
11
Table 159 - Loss of Basic Frame Synchronization Counter with Auto Clear (R/W Address Y16) (E1)
9
8
7
6
5
4
3
2
1
0
SLC15
SLC14
SLC13
SLC12
SLC11
SLC10
Name
SLC9
SLC8
SLC7
SLC6
SLC5
SLC4
SLC3
SLC2
SLC1
SLC0
EEC15
EEC14
EEC13
EEC12
EEC11
EEC10
Name
EEC9
EEC8
EEC7
EEC6
EEC5
EEC4
EEC3
EEC2
EEC1
EEC0
Loss of Basic Frame Synchronization Counter. These bits make up a counter which is
incremented for each 125 us period in which basic frame synchronization (BSYNC=1
status register address Y10) is lost. This counter is cleared by a basic frame
synchronization to a loss of basic frame synchronization state transition (BSYNC=0 to 1),
or with an overflow, a RESET (RESET pin or RST bit), or it may be set by writing the
desired value to it. SLC0 is the least significant bit (LSB).
E-bit Error Counter. These bits make up a counter which is incremented for each
received PCM30 CRC-4 submultiframe E-bit error. This counter is cleared with an
overflow, a RESET (RESET pin or RST bit), or may be set by writing the desired value to
it. EEC0 is the least significant bit (LSB).
Table 160 - E-bit Error Counter (R/W Address Y17) (E1)
Zarlink Semiconductor Inc.
MT9072
188
Functional Description
Functional Description
Data Sheet

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