mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 97

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

15.1
All 33 interrupt status registers are maskable with 33 corresponding interrupt mask registers. All interrupt status
registers and all interrupt mask registers are 16 bits, although all 16 bits are not always used. Unused status bits
may be either one or zero if read.
When an unmasked interrupt occurs, one or more bits of the 33 interrupt status registers will go high causing one or
more bits of the unmasked interrupt vector to go high. A high bit in the interrupt vector causes the output IRQ pin to
go low (if enabled by SPND, INTA control bits). After an interrupt status register is read, it is automatically cleared.
After all interrupt status registers are cleared, the interrupt vector is cleared causing the IRQ pin to return to a high
impedance state.
If a new unmasked interrupt occurs while the interrupt status registers from a previous interrupt are being read, the
affected interrupt status registers will be updated, the interrupt vector will be updated, and the IRQ pin will remain
low until all interrupt status registers are cleared.
If the interrupt status registers are unmasked, and the interrupt vector is masked, the interrupt status registers will
function normally, but they will not cause the IRQ pin to toggle low. Only set bits in the Interrupt Vector will cause the
IRQ pin to toggle low. This is similar to the SPND control bit function, but instead of masking all selected framer
interrupts, the interrupt vector mask can mask individual registers within the selected framers.
15.1.1
SPND - All interrupts for a particular framer may be suspended without changing the interrupt mask words, by
setting the
be updated (and will be cleared when read), but the selected framers interrupt vector bits will remain at zero.
Therefore that framer cannot toggle the IRQ pin. If all eight framer’s SPND bit are zero, then all interrupt vector bits
will remain low, therefore none of the framers can toggle the IRQ pin.
In some applications, a logic low at the IRQ pin lasting the full duration of the interrupt service routine may be
undesirable. In these cases, immediately following the interrupt, set the control bit SPND (register address YF1) low
until the interrupt service routine is finished
INTA - All interrupt and latched status registers for a particular framer may be cleared (without reading the interrupt
status registers) by setting the INTA control bit (register address YF1) to zero. Interrupt status and latched registers
for a particular framer will be cleared (and not updated) as long as INTA is low. Consequently, the selected framer’s
interrupt vector bits will remain at zero, therefore that framer cannot toggle the IRQ pin.
TAIS - During initial power up, all (8 framers) interrupt status registers are cleared without changing the interrupt
mask words, when the TAIS control pin is held low. Consequently, the interrupt vector will remain clear and the IRQ
pin will remain in a high impedance state. This allows for system initialization without spurious interrupts. Interrupt
status registers will not be updated, and the IRQ pin will be forced to a high impedance state as long as TAIS is low.
RESET or RST - After a MT9072 reset (RESET pin for all eight framers or RST control bit (register address YF1)
for a selected framer), all interrupt status register bits are unmasked, but the SPND and INTA control bits are set to
zero.
15.2
There are two common methods for identifying the source of an interrupt. The Polling Method is the simplest but
uses the most processor time. The Vector Method requires a two step process, but uses the least amount of
processor time.
Interrupt Status Register Overview
Interrupt Servicing Methods
Interrupt Related Control Bits and Pins
SPND
control bit (register address YF1) to zero. All unmasked interrupt status registers will continue to
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MT9072
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Data Sheet