mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 148

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

15-8
7 - 0
15-8
15-9
7 - 2
7-0
Bit
Bit
Bit
8
1
0
(00000000)
(00000000)
(0000000)
ADRM16
ADRM11
(000000)
ADRM10
CNT7-0
ADM26
ADM20
BIT7-0
Name
Name
Name
A2EN
A1EN
(0)
(0)
(0)
#
#
-
-
Address Mask 26 to Address Mask 20. A seven bit mask used to interrogate the second
byte of the received address. Adr26 is the MSB. This mask is ignored (as well as first byte
mask) if all call address (1111111) is received.
Address 2 Enable. When this bit is high, this seven bit mask is used in address
comparison of the second address byte. If address recognition is enabled, any packet
failing the address comparison will not be stored in the RX FIFO. A2en must be high for
All-call address recognition. When this bit is low, this bit mask is ignored in address
comparison
Address Mask 16 to Address Mask 11.A six bit mask used to interrogate the first byte of
the received address. AdrM16 is MSB.
Address 10 Mask.This bit is used in address comparison if a seven bit address is being
checked for (YF2 bit ’Seven’ is set).
Address 1 Enable.When this bit is high, this six (or seven) bit mask is used in address
comparison of the first address byte.
If address recognition is enabled, any packet failing the address comparison will not be
stored in the RX FIFO. A1en must be high for All-call (1111111) address recognition for
single byte address. When this bit is low, this bit mask is ignored in address comparison.
not used.
This eight bit word is tagged with the two status bits from control register 1 (EOP and FA),
and the resulting 10 bit word is written to the TX FIFO. The FIFO status is not changed
immediately after a write or read occurs. It is updated after the data has settled and the
transfer to the last available position has finished. Note that when the HDLC is connected
to a T1 channel, the least significant bit in the FIFO
is sent first.
not used.
The Transmit Byte Count Register indicating the length of the data portion of the packet
about to be transmitted. This is the size of the data and not the address, flags or FCS. The
Transmit Byte Counter position Y1C determines the number of bytes that have been sent
from the Transmit FIFO.
Table 115 - Address Recognition Register(YF4) (T1)
Table 117 - TX Byte Count Register(YF6) (T1)
Table 116 - TX Fifo Write Register(YF5) (T1)
Zarlink Semiconductor Inc.
MT9072
148
Functional Description
Functional Description
Functional Description
Data Sheet