mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 267

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mt9072av2

Manufacturer Part Number
mt9072av2
Description
Octal T1/e1/j1 Framer
Manufacturer
Zarlink Semiconductor
Datasheet

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AC Electrical Characteristics - Receive Data Link Timing
1
2
3
RXDL
Bit Cells
E2i
RxDLC - Note 2
(Output)
RxDLC - Note 3
(Output)
RxDL
(Output)
Note 1 - RxDLC output applies for every second frame (RxBF) pulse (250us) only
Note 2 - Clock output provided by setting control bit DLCK=1 (register address Y08)
Note 3 - Enable output provided by clearing control bit DLCK=0 (register address Y08)
Note 4 - The PCM 30 Timeslots are with respect to RXDL Output
Clock Delay
Enable Delay
Data Delay Read
Characteristics
t
ED
t
DDR
Figure 68 - Receive Data Link Timing
Sym.
t
Outputs Data
Zarlink Semiconductor Inc.
t
t
t
DDR
CD
CD
ED
MT9072
MT9072
Min.
267
Typ.
t
t
CD
ED
Max.
125
55
55
Units
ns
ns
ns
150 pF load on RxDLC
150 pF load on RxDLC
150 pF load on RxDL
Test Conditions
Data Sheet
V
V
V
V
T
T
T
T

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