mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 58

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

7.1.1
When EDLEN(Y06) is set to "1" the data link (DL) bits can be sourced/sinked to and from the TxDL and RxDL pins,
by enabling the corresponding pulses in either gapped clocks or enable low signals provided at the RxDLC and
TxDLC pins. The option of either gapped clock or enable signal is selected by control bit DLCK (Register address
Y06).
In D4 or ESF mode, the optional serial data link operates at 4 khz. In D4 mode the data link pins are used to
send/receive Fs bits only, while the Ft bits are generated internally. See Figures 40 to 43.
7.1.1.1
The RxDLC clock is derived from the receive extracted clock (EXCLi).The B8ZS decoded receive data, at
1.544 Mbit/s, is clocked out of the device on the RxDL pin with the rising edge of EXCLi and is aligned to RXDLC. In
order to facilitate the attachment of this data stream to a Data Link controller, the clock signal RxDLC (falling edge
of EXCLi) consists of positive pulses, of nominal width of 344 ns, during the Fs bit cell times that are selected for the
Data Link, with the rising edge aligned with the middle of the bit cell. DL data will not be lost or repeated when a
receive frame slip occurs as the DL data does not pass through the elastic buffer. See Figures 42 to 43 for timing
requirements.
7.1.1.2
The TxDLC clock is derived from the transmit clock (TXCL) and is provided one frame before its usage on the
appropriate S-bit. Hence the TXDLC clock is provided one frame before it is used in ESF Mode in Frames 2, 4, 6, 8,
10, 12, 14, 16, 18, 20, 22, 24. See Figures 40 to 41 for timing requirements.
Register
Address
Y06
Y07
Y08
Y12
Y25
Y35
Y45
T1 Data Link (DL) Pin Access
T1 Data Link (DL) Pin Data Received from PCM24
T1 Data Link (DL) Pin Data Sent to PCM24
HDLC and Data Link Control
Register
Transmit bit Oriented Message This register holds the message that will be sent in ESF FDL if the
Receive bit Oriented Message
Match
Receive bit Oriented Message This register holds the value of the receive bit oriented message
Receive Line Status and Timer
Latch
Receive Line and Timer
Interrupt Status
Receive Line and Timer
Interrupt Mask
Table 16 - Registers Related to the Data Link and Bit Oriented Messages (T1)
Register
This register determines the source of the Data Link which can be
the HDLC, Bit Oriented messages or the external Data Link. This
register also controls the type of clocks provided to the external
Data Link interface.
BOMEN bit in Y06 is set.
This register is the match register for received bit oriented message
This register contains bit oriented message and bit oriented
message match latch bits.
This register contains bit oriented message and bit oriented
message match interrupt status bits.
These are the mask bits for Y35.
Zarlink Semiconductor Inc.
MT9072
58
Description
Data Sheet