mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 223

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

Bit
Bit
15
14
13
12
11
10
1
0
9
8
7
6
F0RVS
F0SVS
F7HVS
F7EVS
F7RVS
F7SVS
F6HVS
F6EVS
F6RVS
F6SVS
F5HVS
F5EVS
Name
Name
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Framer 0 Rx Line Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Receive Line status register(035) for Framer 0 are set. This bit can be masked and will remain
low by the F0RM bit in address 902.
Framer 0 Sync Vector Status. This bit if unmasked is set if any of the bits in the Interrupt Sync
status register(034) for Framer 0 are set. This bit can be masked and will remain low by the
F0SM bit in address 902.
Framer 3 HDLC Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
HDLC register(733) for Framer 7 are set. This bit can be masked and will remain low by the
F7HM bit in address 903.
Framer 7 Elastic Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
HDLC register(736) or Elastic store status for Framer 7 are set. This bit can be masked and will
remain low by the F7EM bit in address 903.
Framer 7 Rx Line Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
HDLC register(735) for Framer 7 are set. This bit can be masked and will remain low by the
F7RM bit in address 903 .
Framer 7 Sync Vector Status. This bit if unmasked is set if any of the bits in the Interrupt HDLC
register(734) for Framer 3 are set. This bit can be masked and will remain low by the F7SM bit
in address 903.
Framer 6 HDLC Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
HDLC register(663) or Elastic store status for Framer 6 are set. This bit can be masked and will
remain low by the F7HM bit in address 903.
Framer 6 Elastic Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Receive Elasitc store register(636) or Elastic store status for Framer 5 are set. This bit can be
masked and will remain low by the F5EM bit in address 903.
Framer 6 Rx Line Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Receive Line status register(635) for Framer 6 are set. This bit can be masked and will remain
low by the F6RM bit in address 903.
Framer 6 Sync Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Counter status register(634) for Framer 6 are set. This bit can be masked and will remain low by
the F6SM bit in address 903.
Framer 3 HDLC Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
HDLC register(533) or Elastic store status for Framer 5 are set. This bit can be masked and will
remain low by the F7HM bit in address 903.
Framer 5 Elastic Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Receive Elasitc store register(536) or Elastic store status for Framer 5 are set. This bit can be
masked and will remain low by the F5EM bit in address 903.
Table 199 - Interrupt Vector 1 Status Register (R/W Address 910) (E1)
Table 200 - Interrupt Vector 2 Status Register (Address 911) (E1)
Zarlink Semiconductor Inc.
MT9072
Functional Description
Functional Description
223
Data Sheet