L64724 LSI Logic Corporation, L64724 Datasheet - Page 101

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

ADC_BP
OB_2C
XCTR
DEMOD_RST
Group 4: Configuration Registers
AD Converter Bypass
When the ADC_BP bit is 1, the dual AD Converter
modules are bypassed and the digital input signals for the
I and Q channel are accepted on the IBYPASS[5:0] and
QBYPASS[5:0] buses, respectively. When the bit is 0, the
AD Converters are active and analog input signals are
accepted on the IVIN and QVIN pins.
Input Format Select
When the OB_2C bit is 0, the input signal to the
demodulator module is assumed to be in offset-binary
format. When the bit is 1, the signal is assumed to be in
two’s-complement format. For operation using the AD
Converters (ADC_BP = 0) OB_2C should be cleared to
0. When the ADC modules are bypassed (ADC_BP = 1),
either format is acceptable through the IBYPASS and
QBYPASS buses.
External Control Output Bits
The value of the XCTR[3:0] field appears on the external
output pins XCTR_OUT[3:0] when the Serial_A bit (APR
62) is 0. When the Serial_A bit is 1, the internal
microcontroller determines the values on the external
output pins XCTR_OUT[3:0]. For more information see
Section 5.10, “External Controls,” page
Appendix C, "Programming the
QPSK Demodulator Software Reset
The L64724 resets the internal datapath and the control
modules for the QPSK Demodulator when the
DEMOD_RST bit is set to 1. The L64724 also resets the
demodulator processing unit and state machines to their
initial states.The FEC Decoder module is not affected.
The bit does not need to be cleared back to 0 to complete
the reset. The L64724 issues a single reset pulse each
XCTR[3:0]
OB_2C
0
1
0
1
Definition
Corresponding output pin = VSS
Corresponding output pin = VDD
Definition
Offset-Binary Format
2’s-Complement Format
Serializer,".
5-23, and
[5:2]
3-71
7
6
1