L64724 LSI Logic Corporation, L64724 Datasheet - Page 186

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

7.4.1 PRBS Generation
7.4.2 Data Alignment With PRBS
7-16
The block diagram of
Figure 7.10 Descrambler Block Diagram
Scrambled
Bit Stream
The following generator polynomial produces the pseudorandom bit
sequence in the Descrambler:
The 15-bit shift register is initialized with a specific value, as shown in
Figure
Figure 7.11 15-Bit Shift Register Initialization
:
The encoder inverts every eighth MPEG transport sync word (0x47) to
generate a sync word (0xB8) that the decoder then uses to align the
Descrambler with the incoming data stream. The first bit of the PRBS is
applied to the first data bit following the inverted MPEG sync byte.
During the following seven noninverted MPEG sync words, the L64724
operates the Descrambler sequence generator, but does not modify the
data stream. The L64724 resets the Descrambler after every inverted
MPEG sync word (see
The FEC Decoder Pipeline
Shift Register Initialization Sequence
1 0 0 1 0 1 0 1 0 0 0 0 0 0 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1
+
x
7.11.
14
+
x
15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 7.10
Figure
Shift Register
7.12).
shows the operation of the PRBS.
XOR
XOR
Descrambled
Bit Stream