L64724 LSI Logic Corporation, L64724 Datasheet - Page 129

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Figure 4.6
ERROROUTn
4.4.1 Parallel Output Interface (SPI_On_Off = 1)
FSTARTOUT
DVALIDOUT
DVALIDOUT
BCLKOUT
(MODE A)
(MODE B)
1. Serial Mode is the recommended interface mode. LSI Logic does not recommend parallel
CO[7:0]
mode for new designs.
Parallel Output Interface Waveforms
You can observe the output of the entire decoding pipeline in parallel
format. Two main modes exist, determined by the SPI_On_Off
configuration bit in Group 4, APR 31, D5.
When the SPI_On_Off bit is set to 1, the parallel output interface outputs
data on CO[7:0] in formats that are similar to the specifications for the
Synchronous Parallel Interface (SPI). The parallel outputs are available
in two modes, Mode A and Mode B. In Mode A, which is similar to mode
2 of SPI, the DVALIDOUT signal is HIGH only during the data bytes and
goes LOW during the RS check bytes. In Mode B, which is similar to the
SPI mode 3, the DVALIDOUT signal always stays HIGH.
The FSTARTOUT strobe signal overlaps the first data byte. When the
SPI_On_Off bit is HIGH, an internal clock generation scheme guarantees
exactly 204 byte clock cycles per packet on the BCLKOUT pin as
required for the DVB frame format. This ensures that the data stream is
devoid of any gaps within a packet boundary and also between packet
boundaries. The data is available on the CO[7:0] pins as a continuous
flow. The L64724 asserts the BCLKOUT signal in the middle of the
decoded data bytes, so the device that receives the output from the
L64724 can latch data at the BCLKOUT rate instead of at the PCLK rate.
Data Output Interface
Byte 0 Byte1 Byte 2
Message
N = Code Word Length
Byte
Check Bytes
1
Byte 0
4-15