L64724 LSI Logic Corporation, L64724 Datasheet - Page 112

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.10 Reset Effect on Register Bits
3-82
This section contains a summary table showing how various reset
operations affect the L64724 register bits. The following reset operation
abbreviations appear in the table:
L64724 Registers
HR–Hardware reset through the L64724 RESET pin.
SF–Software reset for the FEC module (FEC_RST bit).
SD–Software reset for the Demodulator module (DEMOD_RST bit)
UR–Microcontroller reset based on the falling edge of the
Micro_Enable bit (Group 5, APR 520), with the Reset Mode bit
(Group 5, APR 520) cleared to 0.
NR–Not affected by any reset.
microprocessor write operations to Groups 0 to 6 are
disallowed while the on-chip microcontroller is enabled.
The operation can be described as follows: at power-up
the Micro_Enable (Group 5, APR 520) bit is cleared to 0.
The external microprocessor loads register Groups 2 and
4, then loads the micro instructions into Group 5. At this
point, the Micro_Enable bit in Group 5 is set to 1.
If the uC Configuration[2] bit is cleared to 0 (indicating
that arbitration is turned off), further host microprocessor
writes to the uC Configuration and Micro_Enable bits in
Group 5 are not allowed while the on-chip microcontroller
is running. The host microprocessor then shuts off the
on-chip microcontroller by writing to Group 7.
If the uC Configuration[2] bit is set to 1 (indicating that
arbitration is turned on), further host microprocessor
writes to all register groups are allowed, and the host
microprocessor can disable the microcontroller by writing
either to Group 7 or to the Micro_Enable bit in Group 5.