L64724 LSI Logic Corporation, L64724 Datasheet - Page 105

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.45 FMODE, SPI_CLK_AND, SPI_MODE_A_B, and SPI_N
(Group 4: APR 63)
This register is used to configure the SPI Interface.
FMODE
SPI_CLK_AND
SPI_MODE_A_B
Reserved
SPI_N
Group 4: Configuration Registers
APR
63
FMODE
D7
SPI_CLK
BCLK Format
When the FMODE bit is 1, the descrambler byte clock
signal (BCLKOUT) is enabled during the Reed-Solomon
check bytes. When the bit is 0, the BCLKOUT signal is
disabled during check bytes. Enabling SPI (by setting the
SPI_On_Off bit to 1) automatically takes care of setting
the proper values for the FMODE bit. The SPI_On_Off bit
is located in Group 4, APR 31.
SPI_Clock AND’ing
When the SPI_CLK_AND bit is 1, the SPI Byte Clock is
logically AND’ed with the DVALIDOUT signal.
SPI Mode Select5
The SPI_MODE_A_B bit selects between SPI Mode A
(similar to SPI specification mode 2), and SPI Mode B
(similar to SPI specification mode 3). When the bit is 0,
Mode A is selected. When the bit is 1, Mode B is
selected.
Reserved
This bit is reserved for LSI Logic and must be cleared
to 0.
SPI_N
The SPI_N[3:0] bits contain the numerator of the Viterbi
Code rate.
_AND
D6
SPI_MODE
_A_B
D5
Reserved
D4
D3
SPI_N[3:0]
D0
[3:0]
3-75
7
6
4