L64724 LSI Logic Corporation, L64724 Datasheet - Page 266

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

C.3 Programming for Serial Mode (2-Wire Compliant)
C.3.1 Single Data Write
C.3.2 Two Data Writes
C.3.3 Multiple-Data Writes
C-4
To set the serializer in a mode to produce 2-wire compliant signals on
the SDATA (XCTR_OUT[1]) and the SCLK (XCTR_OUT[0]) signal lines,
the Serial_C register (Group 4, APR 62[6:5]) must be programmed to
0b00.
Follow the steps outlined below to address the slave and perform
subsequent write cycles to it.
1. Write TXSD (7-bit slave address)
2. Wait (11 SCLK cycles)
3. Write TXED (8-bit data)
1. Write TXSD (7-bit slave address)
2. Wait (11 SCLK cycles)
3. Write STXD (8-bit data)
4. Wait (11 SCLK cycles)
5. Write TXED (8-bit data)
1. Write TXSD (7-bit slave address)
2. Wait (11 SCLK cycles){
3. For (i =1; i < #data_bytes; i++)
Figure C.1
Programming the Serializer
}
Note:
shows the 2-wire Serializer operation.
Write STXD (8-bit data)
Wait (11 SCLK cycles)
Write TXED (8-bit data)
Only writes to a 2-wire compliant slave can be
accomplished using the Serializer—it does not perform
read operations. Furthermore, the serializer assumes that
the acknowledge signal is generated properly, every 9th
SCLK cycle, by the slave that the Serializer is addressing.