L64724 LSI Logic Corporation, L64724 Datasheet - Page 78

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.14 Mismatching Bits in Sync 2 Tracking Mode (Group 4: APR 15)
3-48
This register is used to set the maximum number of mismatching bits
allowed to declare a match when comparing the data stream to the
reference synchronization word during the tracking phase in the second
synchronization stage.
Read/Write: R/W
Reserved
Auto Rate
Reserved
L64724 Registers
APR
15
Reserved Auto Rate
D7
Reserved
This bit should be cleared to 0 for normal operation.
Viterbi Decoder Automatic Rate Acquisition
The Auto Rate bit, when set to 1, enables automatic
acquisition of the Viterbi code rate for the convolutional
decoder. When DVB mode is selected (APR 2, D6,
DVB_DSS = 0) the set of code rates that are being
considered for automatic acquisition are 1/2, 2/3, 3/4, 5/6
and 7/8. When DSS mode is selected (APR 2, D6,
DVB_DSS = 1) the rates include 2/3 and 6/7. The VCR
bits (APR 3) are disregarded when the Auto Rate bit is
set. The code rate identified by the Auto Rate mechanism
is available under Group 3, APR 14 (Viterbi Coder Rate
Registers). When the Auto Rate bit is 0, the Viterbi code
rate is determined by the contents of the VCR field
(APR 3).
Reserved
The Reserved bits are for internal use only. They should
always be cleared to 0, and produce random results
when read.
D6
Auto Rate
0
1
D5
Reserved
Viterbi Decoder Acquisition Mode
Code rate determined by VCR[2:0]
Automatic Code Rate Acquisition
D4
IMQ_EN DI_Bypass
D3
D2
D1
L[1:0]
D0
[5:4]
7
6