L64724 LSI Logic Corporation, L64724 Datasheet - Page 178

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

7.2 Deinterleaver Module
Figure 7.5
7-8
From
Encoder
Interleaving/Deinterleaving Operation for DVB
M
2M
(B - 1)M
The decoder asserts INTn if the corresponding interrupt enable bit,
VBER_IE, is set in the System Mode Register (Group 2.) Refer to
Section 3.4, “Group 2: System Mode and System Status Registers,”
page
The BER curves to assist in the proper selection of the ratio of the
threshold values VMDC1 and VBERC are shown in
Decoder Synchronization,” page
Figure 7.5
mode.
The Interleaver is a device that rearranges the ordering of a sequence
of symbols in a deterministic manner. A (B, N) Periodic Interleaver has
the following characteristics:
This scheme is also known as a convolutional Interleaver/Deinterleaver.
The FEC Decoder Pipeline
The minimum separation at the Interleaver output is B symbols for
any two symbols that are separated by less than N symbols at the
Interleaver input.
If the channel inserts any burst of less than B errors, single errors
occur at the Deinterleaver output.
3-9, for details.
shows the interleaving/deinterleaving operation for the DVB
CHANNEL
6-2.
M
2M
(B - 1)M
Section 6.2, “Viterbi
To
Decoder