L64724 LSI Logic Corporation, L64724 Datasheet - Page 47

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.4.2 System Status Register (STS)
Table 3.3
APR
0
1
2
3
CLK_LK
VBER
uC_I7
D7
Group 2 System Status Register Map (Read-Only)
CLK_LLK
S3_LS
uC_I6
uC_IE1
uC_IE0
The STS Register is a read-only register that provides the external
microprocessor access to L64724 status information.
the STS map.
The STS register bits indicate the event that generated an internal
interrupt condition. The interrupt status bits are set regardless of the
enable interrupt bits in the SMR Register. The internal status is updated
every L64724 CLK. When the microprocessor reads the status, the
current information is buffered in a special-purpose 32-bit STS buffer that
locks the STS value until the end of the microprocessor read operation.
Group 2: System Mode and System Status Registers
D6
CP_LK
uC_I5
S3_S
D5
Reserved
uC Interrupt 1 Enable
The microprocessor sets the uC_IE1 bit to enable
interrupt 1 from the on-chip microcontroller. The
microcode can define the meaning of interrupt 1;
therefore, this is a user-programmable interrupt.
uC Interrupt 0 Enable
The microprocessor sets the uC_IE0 bit to enable
interrupt 0 from the on-chip microcontroller. The
microcode can define the meaning of interrupt 0;
therefore, this is a user-programmable interrupt.
CP_LLK
S2_LS
uC_I4
D4
STS[23:16]
STS[31:24]
STS[15:8]
STS[7:0]
uC_I3
S2_S
D3
Set to 0
S1_LS
uC_I2
D2
TL_CL_FS_
CL_FS_LL
uC_I1
S1_S
D1
LL
Table 3.3
TL_CL_FS_
CL_FS_UL
Reserved
uC_I0
shows
D0
UL
3-17
25
24