L64724 LSI Logic Corporation, L64724 Datasheet - Page 119

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

The example values for PLL_S, PLL_N, PLL_T, and PLL_M to cover the
frequency range from 2 to 90 MHz for PCLK based on a 15 MHz external
source and a 4 MHz source are tabulated in
formula used for these tables is shown in
Equation 4.2
The PLL_M value selects the minimum and maximum VCO range.
Table 4.1
PLL Clock Generation
(Sheet 1 of 4)
PLL_S
[5:0]
Fpclk
12
58
46
34
56
22
54
32
42
62
10
58
38
28
46
18
=
Fxtal
PLL_N
Parameters for Crystal Clock (CLK) = 15 MHz
[5:0]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
----------------------------------------- -
PLL_N PLL_T
PLL_S
PLL_T
[4:0]
10
10
10
12
12
10
2
8
6
4
6
8
2
8
6
4
PLL_M
[1:0]
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
Equation
VCO (min)
Table 4.1
70
70
70
70
70
70
70
70
70
70
70
70
70
60
60
60
4.2.
and
(max)
VCO
Table
90
90
90
85
85
85
85
85
85
85
85
85
85
70
70
70
4.2. The
PCLK
90.00
87.00
86.25
85.00
84.00
82.50
81.00
80.00
78.75
77.50
75.00
72.50
71.25
70.00
69.00
67.50
4-5