L64724 LSI Logic Corporation, L64724 Datasheet - Page 280

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Table E.1
E-4
Mnemonic
ASA
DECLP
BR
SKZ
SKNZ
WTSYMBS
(Sheet 3 of 3)
L64724 C Instruction Set (Cont.)
Expansion
Arithmetic
Shift Acc
Decrement
Loop Control
Register
Branch
Skip on Zero
Skip on
Non-Zero
Wait valid
demod
symbols
L64724 On-chip Microcontroller
Opcode
[11:8]
1010
1011
1100
1101
1110
1111
Relative 8-bit
complement
address in
instruction
Datafield
xxxxxabc
xxxxxxab
abcdefgh
abcdefgh
unsigned
two’s
[7:0]
8-bit
Description
Arithmetic shift to accumulator value,
according to bits abc in instruction’s
datafield.
a = direction of shift
0 = left shift with zero padding
1 = right shift with sign extension
bc = amount of shift
00 = 1-bit shift
01 = 2-bit shift
10 = 4-bit shift
11 = 8-bit shift
The sign bit = acc(23) retains its value dur-
ing all right and left arithmetic shifts.
Decrement specified scratch pad register
dedicated for loop control.
00 = decrement LP0
01 = decrement LP1
10 = decrement LP2
Branch to the specified uC program line.
The relative branching address is given in
the instruction’s data field. Jump to relative
address + 1.
Skip the next instruction if the result of
applying the specified and-or mask on the
accumulator’s low byte results in a logical
zero.
acc[7:0] = acc[7:0], in other words, its value
is not affected by the SKZ instruction.
Skip the next instruction if the results of
applying the specified mask on the accumu-
lator’s low byte results in non-zero.
acc[7:0] = acc[7:0], i.e. its value is not
affected by the SKNZ instruction
Wait until timer count down completed, the
timer counts valid demod symbols.
Formula for number of clk cycles it takes for
this instruction is to be included.