L64724 LSI Logic Corporation, L64724 Datasheet - Page 213

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

A.4 Read Cycle Using the Serial Bus Interface
Please refer to
steps must take place for a read cycle:
1. The master starts the cycle by issuing a start condition.
2. The master transmits the 7-bit slave address.
3. The master sets the R/W bit = 0 to indicate a write cycle.
4. The addressed slave acknowledges the reception of the slave
5. The Master sends the 8-bit Group 0 address (0x0) to indicate that
6. The master then sends the 8-bit data. This data is used to initialize
7. The master does a repeat start condition.
8. The master transmits the 7-bit slave address.
9. The master sets the R/W bit = 0 to indicate a write cycle.
10. The addressed slave acknowledges the reception by driving D[1]
11. The master transmits the number of the group that it wishes to read
12. The master issues another start condition.
13. The master transmits the 7-bit slave address.
14. The master sets the R/W bit = 1 to indicate a read cycle.
15. The slave drives D[1] LOW to acknowledge.
16. The slave starts transmitting the data, MSB first.
17. The master has to provide the acknowledge by driving D[1] LOW
18. In the case of a single read, the master does not drive D[1] LOW
19. The master terminates the cycle by issuing a stop condition.
Read Cycle Using the Serial Bus Interface
address by driving D[1] LOW in the ACK cycle.
the APR is to be loaded. Group 0 is accessed only to load the APR.
the base pointer (APR0/1).
LOW in the ACK cycle.
(which is acknowledged by the slave).
during the ACK cycle.
during the ACK cycle after reception of the first byte. The slave
responds to this by relinquishing control of the bus and waiting for
the master to issue a stop condition. For burst reads, the master
drives D[1] LOW for each byte it receives during the ACK cycle,
except for the last byte.
Figure A.6
for a burst or a single read cycle. The following
A-7