L64724 LSI Logic Corporation, L64724 Datasheet - Page 50

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3-20
APR
1
CLK_LK
D7
CLK_LLK
S1_S
Reserved
The following register diagram shows the bit organization of STS[15:8].
Descriptions of the bits follow the register diagram.
CLK_LK
CLK_LLK
L64724 Registers
D6
CP_LK
D5
Stage 1 Synchronization Flag
The L64724 sets the S1_S bit when the Viterbi Decoder
synchronization module has acquired synchronization.
The L64724 also generates an interrupt if the S1_S_IE
bit is set in the SMR. The L64724 clears S1_S to 0 after
a reset or a Group 2 (STS) read.
Reserved
This bit is reserved for LSI Logic internal use only.
Reading this bit will give unpredictable results.
Timing Lock Established
The L64724 sets the CLK_LK bit when Timing Lock is
established.
Timing Lock Lost
The L64724 sets the CLK_LLK bit when Timing Lock is
lost.
CLK_LLK
CLK_LK
S1_S
CP_LLK
0
1
0
1
0
1
D4
STS[15:8]
Definition
Stage 1 Synchronization status unchanged
Stage 1 Synchronization acquired
Definition
Timing Lock Status Unchanged
Timing Lock Established
Definition
Timing Lock Status Unchanged
Timing Lock Lost
D3
Reserved = 0
D2
CL_FS_LL
D1
CL_FS_UL
D0
15
14
1
0