L64724 LSI Logic Corporation, L64724 Datasheet - Page 72

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.6 Viterbi Max Data Bit Count 2 (Group 4: APR 5, 6, and 7)
3.6.7 Viterbi Maximum Bit Error Count, Rate 1/2 (Group 4: APR 8)
3-42
For more information see
Read/Write: R/W
These registers specify the number of valid symbols, divided by four, over
which the number of symbol errors in the Viterbi output data stream are
counted, after synchronization. The symbol error count is then displayed
as VBERC (Group 3, APR 4,5). The value for VMDC2 occupies 24 bits
and is arranged as three bytes with APR 5, bit 0 being the least
significant bit and APR 7, bit 7 being the most significant bit. For
example, a value of VMDC2[23:0] = 0x00.00F0 specifies 960 data bits.
Equation 3.2
For more information see
Read/Write: R/W
This register specifies the maximum number of Viterbi symbol errors that
are allowed to occur within the data period set by VMDC1 (Group 4,
APR 4) to achieve Viterbi module synchronization.
L64724 Registers
APR
APR
APR
APR
4
5
6
7
VMDC2
D15
D23
D7
D7
=
Symbols
------------------------ -
Viterbi Maximum Data Bit Count 2, Middle Byte, VMDC2[15:8]
Viterbi Maximum Data Bit Count 2, High Byte, VMDC2[23:16]
Viterbi Maximum Data Bit Count 2, Low Byte, VMDC2[7:0]
4
Viterbi Maximum Data Bit Count 1, VMDC1[7:0]
Section 7.1.3, “Viterbi BER Monitor,” page
Section 7.1.3, “Viterbi BER Monitor.”
D16
D0
D0
D8
7-7.