L64724 LSI Logic Corporation, L64724 Datasheet - Page 261

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Table B.14
(Sheet 3 of 4)
APR
[5:0]
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Reserved
SWP_
SWAP
SWP_
SWAP
CAR_
SNR_
CLK_
EST
D7
Low Data Rate Register Values (Cont.)
CLK_LAMBDA_SEL[3:0]
Clock Loop Lambda,
ERROR
ERROR
PWRP_
_SWAP
_SWAP
QPSK Demodulator and FEC Configuration Example: Low Data Rates
CAR_
CLK_
TRI
D6
Carrier Loop Filter Initialization, CAR_LF_INIT[23:16]
Carrier Loop Filter Initialization, CAR_LF_INIT[15:8]
Carrier Loop Filter Initialization, CAR_LF_INIT[7:0]
Carrier Upper Sweep Limit, CAR_USWL[15:8]
Carrier Lower Sweep Limit, CAR_LSWL[15:8]
Carrier Lower Sweep Limit, CAR_LSWL[7:0]
Clock Upper Sweep Limit, CLK_USWL[15:8]
Clock Lower Sweep Limit, CLK_LSWL[15:8]
Clock Upper Sweep Limit, CLK_USWL[7:0]
Clock Lower Sweep Limit, CLK_LSWL[7:0]
AUTO_
AUTO_
Clock Sweep Rate, CLK_SWR[15:8]
CAR_
Clock Sweep Rate, CLK_SWR[7:0]
Clock Loop Bias, CLK_BIAS[23:16]
ADC_
CLK_
SWP
SWP
Clock Loop Bias, CLK_BIAS[15:8]
Clock Loop Bias, CLK_BIAS[7:0]]
PD
D5
Clock Loop Bias, CLK_BIAS[30:24]
Set to 1
LOCK_
LEN
FP_
D4
Reserved
PWRP
AGC_
CLK_
SEL
D3
Reserved
CLK_MU_SEL[3:0]
CAR_
PED_
Clock Loop Mu,
SEL
D2
Reserved
OPEN
OPEN
CAR_
CLK_
D1
ALPHA
CAR_
CLK_
CLK_
_SEL
DO
SW
SW
HEX
CC
EE
6D
C0
FB
F7
78
39
00
65
99
28
40
09
00
00
00
00
38
00
B-47