L64724 LSI Logic Corporation, L64724 Datasheet - Page 86

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.21 Clock Divider 2 (Group 4: APR 22, 23)
3.6.22 Power Reference Level (Group 4: APR 24)
3-56
This register is used to set the division ratio for the generation of LCLK.
Read/Write: R/W
DC_Offset_On_Off
Reserved
CLK_DIV2
Read/Write: R/W
L64724 Registers
APR
APR
APR
24
22
23
D15
D7
D7
DC_Offset_On_
Off[1:0]
DC Offset On Off[15:14]
The DC_Offset_On_Off[1:0] bits control the DC offset
circuit as shown in the following table.
Reserved
The Reserved bit must always be cleared to 0, and
produces random results when read.
Input Division Factor for LCLK
The frequency of the output signal LCLK is determined
by the value of CLK_DIV2[12:0] as follows:
LCLK = CLK/CLK_DIV2[12:0].
DC_Offset_
On_Off[1]
D14 D13
0
1
1
Reserved
DC_Offset_
On_Off[0]
PWR_REF[7:0]
CLK_DIV2[7::0]
D12
X
0
1
Definition
DC_Offset OFF
DC_Offset On;
Noise Feedback Off
DC_Offset On;
Noise Feedback On
CLK_DIV2[12:8]
[7:0], [12:8]
D0
D0
D8
13