L64724 LSI Logic Corporation, L64724 Datasheet - Page 158

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Figure 6.1
Data
6.2 Viterbi Decoder Synchronization
6-2
Module
Viterbi
Sync.
Synchronization
Viterbi Decoder
In Sync/
Out of Sync
Bit Error Monitor
First Stage
Synchronization Module
Data
Decoder
Viterbi
This section describes the first stage of the Synchronization module,
which performs Viterbi Decoder synchronization.
In the first stage, the decoder observes the valid data symbols and bit
errors in the decoded data stream to determine the in- or out-of-
synchronization condition. The Viterbi Max Data Bit Count Registers
(VMDC1 in Group 4, APR 4, and VMDC2 in Group 4, APR 5–7) set the
number of valid data bits at the output of the Viterbi Decoder over which
the decoder counts channel symbol errors. During that interval,
whenever the bit error count is above the value specified in the Viterbi
Max Data Bit Error Count Register (Group 4, APR 8–13,) the
synchronization logic flags an out-of-synchronization condition.
Figure 6.2
Decoding Pipeline Synchronization
Viterbi
Control
Data
shows the Viterbi Decoder synchronization.
Module
RS/DI
Sync.
In Sync/
Out of Sync
Reed-Solomon Deinterleaver
Data
Global Control
Synchronization
Second Stage
leaver
inter-
De-
DI
Control
Signals
Data
Configuration Parameters
Decoder
RS
RS
Control
Data
Module
Descr.
Sync.
In Sync/
Out of Sync
Synchronization
Data
Descrambler
Third Stage
Descrambler
Descrambler
Control
Data