L64724 LSI Logic Corporation, L64724 Datasheet - Page 95

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.36 Clock Synchronizer Sweep Rate (Group 4: APR 43 and 44)
3.6.37 Clock Synchronizer Sweep Upper Limit
(Group 4: APR 45 and 46)
CLK_MU_SEL
This register determines the Clock Synchronizer sweep rate.
Read/Write: R/W
CLK_SWR
Read/Write: R/W
CLK_USWL
Group 4: Configuration Registers
APR
APR
APR
APR
43
44
45
46
D15
D15
D7
D7
Clock Loop Mu
Program the CLK_MU_SEL[3:0] bits with values that set
the parameters of the clock recovery loop. For details,
see
Modes,” page 5-9.
Clock Synchronizer Sweep Rate
CLK_SWR[15:0] is a signed, two’s complement number.
For details, see
Equations and Timing Loop Bias,” page 5-11.
Clock Sweep Upper Sweep Limit
Program the CLK_USWL[15:0] register to set the upper
limit of the frequency sweep. For details, see
5.6.1.2, “Timing Loop Sweep Equations and Timing Loop
Bias,” page
complement number.
Section 5.6.1, “Clock Acquisition and Tracking
5-11, CLK_USWL[15:0] is a two’s
Section 5.6.1.2, “Timing Loop Sweep
CLK_USWL[15:8]
CLK_SWR[15:8]
CLK_USWL[7:0]
CLK_SWR[7:0]
Section
[15:0]
[15:0]
D0
D8
D0
D8
[3:0]
3-65