L64724 LSI Logic Corporation, L64724 Datasheet - Page 84

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.19 Clock Loop Control 2 (Group 4: APR 20)
3-54
The Clock Loop Control 2 register sets the matched filter roll-off factor,
used in the Demodulator Module PLL. The register also contains the
power down control bit.
Read/Write: R/W
Reserved
PD
Reserved
MF_20_35
L64724 Registers
APR
20
D7
Reserved
Reserved
These Reserved bits must be cleared to 0 for proper
operation.
Power Down
When you set the PD bit to 1, all modules except the
asynchronous microprocessor interface are turned off to
minimize power consumption. No data processing occurs
during power down. When you clear the PD bit to 0, all
elements operate. You should apply a reset pulse after
you change the PD bit from 1 to 0 (wake-up) before you
start processing data.
Reserved
These Reserved bits must be cleared to 0 for proper
operation.
Matched Filter Roll-Off Factor
The MF_20_35 bit, when set to 1, selects a roll-off factor
of 0.35 for the matched filter in accordance with the DVB
specifications. When the MF_20_35 bit is 0, a 0.20 roll-
off factor is selected for DSS systems.
MF_20_35
PD
0
1
0
1
D5
PD
D4
Definition
Normal Operation
Device in Power Down Mode
Matched Filter Roll-Off Factor
D3
Reserved
0.20
0.35
D1
MF_20_35
D0
[7:5]
[3:1]
4
0