L64724 LSI Logic Corporation, L64724 Datasheet - Page 284

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Table E.2
E-8
(Sheet 4 of 5)
Group 4
(Cont.)
C_ADD
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
Microcontroller Address Map (Cont.)
L64724 On-chip Microcontroller
P_APR
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
SWAP
SWAP
SWP_
SWP_
CAR_
SNR_
CLK_
EST
Res
D7
CLK_LAMBDA_SEL[3:0]
Carrier Loop Filter Initialization, CAR_LF_INIT[23:16]
Clock Loop Lambda,
Carrier Loop Filter Initialization, CAR_LF_INIT[15:8]
Carrier Loop Filter Initialization, CAR_LF_INIT[7:0]
Reserved
ERROR
ERROR
PWRP_
Carrier Upper Sweep Limit, CAR_USWL[15:8]
_SWAP
_SWAP
Carrier Lower Sweep Limit, CAR_LSWL[15:8]
Carrier Upper Sweep Limit, CAR_USWL[7:0]
Carrier Lower Sweep Limit, CAR_LSWL[7:0]
Clock Upper Sweep Limit, CLK_USWL[15:8]
CAR_
Carrier Frequency Lock Detector Threshold,
Clock Lower Sweep Limit, CLK_LSWL[15:8]
CLK_
Clock Upper Sweep Limit, CLK_USWL[7:0]
Clock Lower Sweep Limit, CLK_LSWL[7:0]
TRI
D6
Carrier Sweep Rate, CAR_SWR[15:8]
Carrier Sweep Rate, CAR_SWR[7:0]
Clock Sweep Rate, CLK_SWR[15:8]
Clock Sweep Rate, CLK_SWR[7:0]
Clock Loop Bias, CLK_BIAS[23:16]
Clock Loop Bias, CLK_BIAS[15:8]
Clock Loop Bias, CLK_BIAS[7:0]]
CAR_
ADC_
Auto_
Auto_
CLK_
SWP
Clock Loop Bias, CLK_BIAS[30:24]
SWP
PD
D5
CAR_LCF_THSL[7:0]
CLK_LC_THSL
AGC_
Input_
LOCK
_LEN
FP_
D4
sel
Threshold, CAR_LCF_THSL[12:8]
Carrier Frequency Lock Detector
[1:0]
PWRP
jit_flr_
Tim_
D3
en
CLK_MU_SEL[3:0]
Clock Loop Mu,
CAR_
Lock_
CLK_
PE_
SEL
PE_
SEL
Test
D2
F_
CAR_
CLK_
TED_
Sym_
Open
Open
SWP
D1
CAR_
ALPH
CLK_
CLK_
SEL
SW
SW
DO
A_
R/W
R/W
by
C