L64724 LSI Logic Corporation, L64724 Datasheet - Page 210

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

A.2 Programming the Slave Address Using the Serial Bus
A.3 Write Cycle Using the Serial Bus Interface
A-4
Interface
A general call address operation on the serial bus is indicated when the
master generates a start condition followed by eight zeroes (see
Figure
the serial bus. Any device that requires information to be supplied
through this general call structure should acknowledge the cycle (see
Figure
The second byte, when set to 0b00000110, indicates a reset and a
hardware write of the programmable part of the slave address. The
L64724 must read the D[3:2] pins, which form the two LSBs of the slave
address. The D[3:2] pins are unused when the serial interface is in use,
and can be hardwired to any of the four possible combinations.
Figure A.4
S: Start Condition
A: Acknowledge Cycle
Refer to
must take place for a write cycle:
1. The master starts the cycle with the start condition.
2. The master transmits the 7-bit slave address.
3. The master transmits the eighth bit (R/W) cleared to 0 to indicate a
4. The addressed slave acknowledges the reception of the slave
5. The master sends the 8-bit Group 0 address (0x0) to indicate that
Programming the L64724 Using the Serial Bus Protocol
S
0
General Call Addr.
write cycle.
address by deasserting D[1] (LOW) in the ACK cycle.
the APR is to be loaded. Group 0 is accessed only to load the APR.
0 0 0 0
A.4.) A general call address operation addresses every device on
A.3.)
Figure A.5
General Call Structure
0 0 0
for a burst or a single write cycle. The following steps
A
X
X X X X
X
X 0
A