L64724 LSI Logic Corporation, L64724 Datasheet - Page 258

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

B-44
Set the bits in the Group 4, APR 62 register as shown in
Table B.13
Group 4, APR 63 – Set to 0x63.
Clear the FMODE bit (D7) to 0. Set the SPI_CLK_AND bit (D6) to 1 to
AND the SPI byte clock and the data valid signal. Set SPI_MODE_A_B
to 0 for Mode A. Set SPI_N[3:0] to 3 since the Viterbi Code Rate is 3/4.
Group 4, APR 64–65 – Set to 0x0008.
Set the SPI_GAIN[9:0] to 8 because the oversampling ratio (OR) is 30.
Set Group 4, APR 65 to 0x08 and APR 64 to 0x00.
Group 4, APR 66–68 – Set to 0x066666.
Set the SPI_Bias[22:0] value as shown in
Equation B.65
L64724 Application Notes
Bits
D7
D6 to D5
D4 to D1
D0
Greater than 16
SPIBias
8 to 16
2 to 4
4 to 8
OR
=
Setting
0b0100
Group 4, APR 62 Register Bits
2
--------------------------
24
–
–
–
OR
VCR
less than 10
Acronym
Serial_B
Serial_C[1:0]
SPI_M[3:0]
Serial_A
SPI Gain
50.0
35.0
15.0
Meaning
Refer to
Serializer, for more details.
Refer to
Serializer, for more details.
Denominator of Viterbi Code Rate = 4
(rate = 3/4)
Refer to
Serializer, for more details.
Equation
Appendix C, Programming the
Appendix C, Programming the
Appendix C, Programming the
B.65.
Table
B.13.