L64724 LSI Logic Corporation, L64724 Datasheet - Page 82

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.17 PLL Reset (Group 4: APR 18)
3.6.18 Decimation Filter Control (Group 4: APR 19)
3-52
Reserved
Read/Write: Write Only
Writing any value to APR 18 generates an internal reset pulse for the PLL
module. The L64724 ignores any data on the D[7:0] bus during a write to
this register. You should reset the PLL module before operating it.
The PLL Reset register (APR18) cannot be read.
Read/Write: R/W
The Decimation Filter Control register sets clock parameters related to
the Demodulator module carrier synchronization logic.
L64724 Registers
APR
APR
18
19
D7
D7
DF_SELECT[2:0]
In Serial Channel Output mode, one bit of decoded data
is presented on the CO[0] pin every PCLK cycle. In
Parallel Channel Output mode, one byte of decoded data
is presented on the CO[7:0] channel data out bus every
eight PCLK cycles. When serial mode is selected, the
BCLKOUT pin is forced LOW. When the SPI_On_Off bit
(Group 4, APR 31, bit 5) is a 1, the OF bit is ignored.
Reserved
The Reserved bits must be set to 0 for proper operation.
OF
0
1
D5
CO[7:0] Channel Data Out
Serial Channel Output Mode
Parallel Channel Output Mode
PLL_RESET
DF_GAIN[1:0]
D4
D3
D2
DF_RATIO[2:0]
D0
D0
[4:0]