L64724 LSI Logic Corporation, L64724 Datasheet - Page 224

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

B.3 QPSK Demodulator and FEC Configuration Example:
B-10
High Data Rates
This section gives an example of how to use the microcontroller interface
of the L64724 to configure the QPSK Demodulator and FEC section for
high data rates. No decimation or decimation filtering is performed. The
configuration in the example is optimized for fixed rate operation with the
following parameters:
The registers for this example are configured as shown in the following
subsections. See
settings.
Group 4, APR 0 – Set to 0x81.
Set bit D7 to 1 and clear bit D6 to 0. Based on Section 4.2, set the
PLL_N[5:0] bits (D5 to D0) to 0x01.
Group 4, APR 1 – Set to 0x14.
Clear bits D7 and D6 to 0. Based on section 4.2, set PLL_S[5:0] (D5 to
D0) to 0x14.
L64724 Application Notes
Transmission Rate
DC offset control
ADC Sampling
Viterbi Rate
Parameter
Frequency
Xtal OSC
Model
E
ADC
b
/N
o
Table
B.8, on
Used after A/D, not after Nyquist filter.
42.6 Mbit/s (21.3 Mbaud)
page
Input: 1.0 V p-to-p
B-26, for a summary of the register
15.00 MHz
50 MHz
4.0 dB
Value
DVB
1/2