L64724 LSI Logic Corporation, L64724 Datasheet - Page 254

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

B-40
CLK_MU_SEL[3:0] and CLK_LAMBDA_SEL[3:0] are defined as shown
in
Equation B.59
Equation B.60
Program the four LSBs of APR 42 with 0x9 and the four MSBs of
APR 42 with 0x9.
Group 4, APR 43–44 – Set to 0x28CC.
The value for the clock sweep rate, CLK_SWR[15:0], is set according to
Equation
Equation B.61
Set Group 4, APR 44 to 0x28 and APR 43 to 0xCC.
Group 4, APR 45–46 – Set to 0x0940.
The value for the upper sweep limit, CLK_USWL[15:0], is set as
explained in the following paragraphs. It should be noted that the upper
sweep limit is an approximate value but the approximation to the real
sweep limit is accurate enough. Assume that the upper sweep limit
needed is + 10 kHz. CLK_USWL[15:0] is calculated as shown in
Equation
L64724 Application Notes
Equation B.59
CLK_SWR
CLK_SWR
CAR_MU_SEL
CAR_LAMBDA_SEL
Note:
B.61, assuming a clock sweep rate of 10 kHz/s.
B.62.
=
Group 4, APR 43–48, contain sweep parameters that need
to be programmed only if clock sweep is required. These
parameters have meaning only when the CLK_SW bit (bit
D0 of Group 4, APR 53) is set to a 1.
=
2
------------------------------------------------------------------- -
2
-------------------------------------------------------- -
F s
45
45
60 10
and
=
l og
---------------------------- -
DF_RATIO
10 10
sweeprat e T
Equation
=
2
6
t
l og
1
a
0.125 16
3
2
2
28
----------------------- -
2.0 10
b
B.60.
16
=
1
2
l og
16
2
6
2
=
0.171 e -5 2
l og
2
=
2
10444
68.6 e -4 2
28
(0x28CC)
=
16
9
=
=
0x9
9
=
0x9