L64724 LSI Logic Corporation, L64724 Datasheet - Page 79

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.15 Synchronization States and BCLKOUT Format (Group 4: APR 16)
IMQ_EN
DI_Bypass
L[1:0]
This register is used to select the algorithms used in the synchronization
modules, and which module’s synchronization status will be shown on
the SYNC output pin. The register also selects the frequency of the clock
that will be output on the BCLKOUT pin.
Group 4: Configuration Registers
(I, -Q) Format Resolution Enable
When the IMQ_EN bit is set to 1, the synchronization
mechanism used for the convolutional decoder
automatically resolves phase reflection (I, -Q). In this
case, the polarity of the IMQ bit (APR 2) is disregarded.
When the IMQ_EN bit is 0, the IMQ bit determines the
symbol format.
Deinterleaver Bypass
When set to 1, the DI_Bypass bit causes the Deinter-
leaver module to be bypassed. When the bit is 0, the
deinterleaver functions according to the DVB or DSS
specifications.
Mismatching Bits, Tracking Mode, Sync2
This field is used to set the maximum number of
mismatching bits allowed to declare a match when
comparing eight bits in the data stream to the reference
synchronization word during tracking phase in the second
synchronization stage. The L[1:0] bits can be configured
from 0b00 to 0b10. Higher values of L[1:0] result in a
smaller probability of loss of lock due to random noise.
Lower values result in a higher probability of loss.
IMQ_EN
0
0
1
1
L[1:0]
0
1
0
1
0
1
Symbol Format
Determined by the value of IMQ (APR 2,
D7)
Automatically determined by
synchronization mechanism.
Number of Mismatching Bits
Illegal Value
0
1
2
[1:0]
3-49
3
2